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Analog Devices |
a Dual PWM Fan Controller and Temperature
Monitor for High Availability Systems
ADM1029*
FEATURES
Software Programmable and Automatic Fan Speed
Control
Automatic Fan Speed Control Allows Control
Independent of CPU Intervention after Initial Setup
Control Loop Minimizes Acoustic Noise and Power
Consumption
Remote and Local Temperature Monitoring
Dual Fan Speed Measurement
Supports Backup and Redundant Fans
Supports Hot Swapping of Fans
Cascadable Fault Output Allows Fault Signaling
between Multiple ADM1029s
Address Pin Allows Up to Eight ADM1029s in A System
Small 24-Lead QSOP Package
APPLICATIONS
Network Servers and Personal Computers
Microprocessor-Based Office Equipment
High Availability Telecommunications Equipment
FUNCTIONAL BLOCK DIAGRAM
VCC
PRESENT1
FAULT1
DRIVE1
ADM1029
PWM
CONTROLLER
SERIAL BUS
INTERFACE
SLAVE ADDRESS
REGISTER
FAN 1 STATUS
REGISTER
FAN 1 MIN
SPEED REGISTER
FAN 1 ALARM
SPEED REGISTER
FAN 1 HOT-PLUG
SPEED REGISTER
ADDRESS POINTER
REGISTER
INTERRUPT MASK
REGISTERS
INTERRUPT STATUS
REGISTERS
LIMIT COMPARATOR
VALUE AND LIMIT
REGISTERS
INTERRUPT
MASKING
TACH1
TACH2
PRESENT2
FAULT2
DRIVE2
PWM
CONTROLLER
FAN SPEED
COUNTER
FAN 2 STATUS
REGISTER
FAN 2 MIN
SPEED REGISTER
FAN 2 ALARM
SPEED REGISTER
FAN 2 HOT-PLUG
SPEED REGISTER
G.P. I/O REGISTER
ADC
ANALOG
MUX
REMOTE SENSOR
SIGNAL
CONDITIONING
BANDGAP
REFERENCE
BANDGAP
TEMP SENSOR
SCL
SDA
INT
CFAULT
RESET
GPIO2
AIN1/GPIO1
AIN0/GPIO0
D2+/GPIO6
D2–/GPIO5
D1+/GPIO4
D1–/GPIO3
TMIN/INSTALL
ADD
GND
*Protected by U.S. Patent Numbers 6,255,973 and 6,188,189
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADM1029–SPECIFICATIONS1, 2
(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
Parameter
POWER SUPPLY
Supply Voltage, VCC
Supply Current, ICC
Min Typ
3.0 3.30
1.7
1.5
10
Max
5.5
3.0
60
Unit Test Conditions/Comments
V
mA Interface Inactive, ADC Active
mA ADC Inactive, DAC Active
µA Shutdown Mode
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
Resolution
External Diode Sensor Accuracy
Resolution
Remote Sensor Source Current
±1 ±3
1
±3 ±5
1
90
5.5
°C
°C
°C 0°C ≤ TA ≤ 100°C
°C
µA High Level
µA Low Level
ANALOG-TO-DIGITAL CONVERTER
Total Unadjusted Error, TUE
Differential Nonlinearity, DNL
Power Supply Sensitivity
Conversion Time
Analog Input or Internal Temperature
External Temperature
±1
11.6
185.6
±1
±1
%
LSB
%/ V
ms
ms
Note 3
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
Full-Scale Count
FAN 1 and FAN 2 Nominal Input RPM4
Internal Clock Frequency
8800
4400
2200
1100
56.4 60.0
OPEN-DRAIN DIGITAL OUTPUTS (INT, CFAULT)
Output Low Voltage, VOL
High Level Output Current, IOH
0.1
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Leakage Current, IOH
0.1
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
2.1
500
DIGITAL INPUT LOGIC LEVELS RESET,
GPIO1-6, FAULT1/2, TACH1/2, PRESENT1/2
Input High Voltage, VIH
Input Low Voltage, VIL
2.1
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING5
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU:STA
Start Hold Time, tHD:STA
Stop Condition Setup Time, tSU:STO
–1
20
10
50
4.7
4.7
4
4
±6
255
63.6
0.4
1
0.4
1
0.8
0.8
+1
100
% 60°C ≤ TA ≤ 100°C: VCC = 3.3 V
rpm Divisor = 1, Fan Count = 153
rpm Divisor = 2, Fan Count = 153
rpm Divisor = 4, Fan Count = 153
rpm Divisor = 8, Fan Count = 153
kHz
V IOUT = –6.0 mA, VCC = 3 V
µA VOUT = VCC
V IOUT = –6.0 mA, VCC = 3 V
µA VOUT = VCC
V
V
mV
V
V
µA VIN = VCC
µA VIN = 0
pF
kHz See Figure 1
ns See Figure 1
µs See Figure 1
µs See Figure 1
µs See Figure 1
µs See Figure 1
–2– REV. 0
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