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NUC946ADN
32-BIT ARM926EJ-S BASED MCU
NUC946ADN
32-bit ARM926EJ-S Based Microcontroller
Product Data Sheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ARM926-based system design. Nuvoton
assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice..
For additional information or questions, please contact: Nuvoton Technology Corporation.
Publication Release Date: July 26, 2011
1 Revision: A5
NUC946ADN
Table of Contents
32-BIT ARM926EJ-S BASED MCU
1 GENERAL DESCRIPTION.........................................................................................................5
2 FEATURES ..............................................................................................................................6
3 PIN DIAGRAM ........................................................................................................................9
4 PIN ASSIGNMENT ................................................................................................................10
5 PIN DESCRIPTION ...............................................................................................................14
5.1 PIN DESCRIPTION FOR INTERFACE ............................................................................................ 14
5.2 GPIO SHARE PIN DESCRIPTION............................................................................................... 17
6 FUNCTIONAL BLOCK ............................................................................................................19
7 FUNCTIONAL DESCRIPTION.................................................................................................20
7.1 ARM926EJ-S CPU CORE.................................................................................................... 20
7.2 SYSTEM MANAGER .............................................................................................................. 20
7.2.1 Overview ............................................................................................................... 20
7.2.2 System Memory Map ............................................................................................... 20
7.2.3 Address Bus Generation........................................................................................... 24
7.2.4 AHB Bus Arbitration ................................................................................................ 25
7.2.4.1 Fixed Priority Mode ................................................................................................................ 25
7.2.4.2 Rotate Priority Mode .............................................................................................................. 26
7.2.5 Power-On Setting ................................................................................................... 27
7.2.6 System Booting ...................................................................................................... 28
7.2.7 System Global Control Registers Map......................................................................... 29
7.3 CLOCK CONTROLLER ............................................................................................................ 39
7.3.1 Power management ................................................................................................ 39
7.3.2 Clock Control Registers Map ..................................................................................... 41
7.4 EXTERNAL BUS INTERFACE ..................................................................................................... 56
7.4.1 Overview ............................................................................................................... 56
7.4.2 Functional Description ............................................................................................. 56
7.4.2.1 SDRAM Controller .................................................................................................................. 56
7.4.2.2 SDRAM Components Supported ............................................................................................... 57
7.4.2.3 AHB Bus Address Mapping to SDRAM Bus.................................................................................. 58
7.4.2.4 SDRAM Power-Up Sequence .................................................................................................... 60
7.4.3 EBI Register Mapping .............................................................................................. 60
7.4.4 EBI Register Details ................................................................................................ 61
7.5 ETHERNET MAC CONTROLLER ................................................................................................. 76
EMC Descriptors ................................................................................................................... 77
7.5.1.1 Rx Buffer Descriptor............................................................................................................... 77
7.5.1.2 Tx Buffer Descriptor ............................................................................................................... 81
7.5.2 EMC Register Mapping ............................................................................................. 86
7.5.3 EMC Register Details ............................................................................................... 88
7.5.4 Operation Notes ....................................................................................................132
7.6 GDMA CONTROLLER...........................................................................................................133
Publication Release Date: July 26, 2011
2 Revision: A5
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