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Número de pieza | W78C33B | |
Descripción | 8-BIT MICROCONTROLLER | |
Fabricantes | Winbond | |
Logotipo | ||
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No Preview Available ! Preliminary W78C33B
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C33B microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is functional compatible with the industry standard 80C32 microcontroller series except
the one extra 4-bit bit-addressable I/O port (Port 4).
The W78C33B contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.
The W78C33B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
• 8-bit CMOS microcontroller
• Fully static design
• Low standby current at full supply voltage
• DC-40 MHz operation
• 256 bytes of on-chip scratchpad RAM
• ROMless operation
• 64K bytes program memory address space
• 64K bytes data memory address space
• Four 8-bit bidirectional ports
• One extra 4-bit bidirectional port
• Three 16-bit timer/counters
• One full duplex serial port
• Boolean processor
• Six-source, two-level interrupt capability
• Built-in power management
• Packages:
− PLCC 44: W78C33BP-24/40
− QFP 44: W78C33BF-24/40
− TQFP 44: W78C33BM-24/40
Publication Release Date: June 1998
- 1 - Revision A1
1 page Preliminary W78C33B
FUNCTIONAL DESCRIPTION
The W78C33B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different instruction and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature
of the W78C33B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78C33B is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C33B relatively insensitive to duty
cycle variations in the clock.
Crystal Oscillator
The W78C33B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
Publication Release Date: June 1998
- 5 - Revision A1
5 Page Preliminary W78C33B
Timing Waveforms, continued
Data Read Cycle
XTAL1
ALE
PSEN
PORT 2
PORT 0
RD
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
A0-A7
A8-A15
TDAR
TDDA
DATA
TDDH, TDDZ
TDRD
Data Write Cycle
XTAL1
ALE
PSEN
PORT 2
PORT 0
WR
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
A0-A7
A8-A15
DATA OUT
TDAD
TDWD
TDAW
TDWR
- 11 -
Publication Release Date: June 1998
Revision A1
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet W78C33B.PDF ] |
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