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Samsung semiconductor |
KS0071B
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
The KS0071B is a dot matrix LCD controller & driver LSI which is fabricated by low power CMOS technology,
designed to drive a split screen dot matrix LCD display of 1 line 24 characters or 2 line 24
characters with 57 dots format.
FEATURES
• Character type dot matrix single chip LCD controller & driver
• High voltage LCD driver 32 common and 60 segment signal output.
• Easy interface with a 4 bit or 8 bit MPU.
• Internal memory
-. Character generator ROM : 8400bits ( 240 characters for 57 dots )
-. Character generator RAM : 512 bits ( 8 patterns for 57 dots )
-. Display data RAM : 640 bits ( 808 bits for 80 characters )
• Maximum display characters
-. 1 line, 1/16 duty, 57 dots + cursor, 24 characters.
-. 2 line, 1/32 duty, 57 dots + cursor, 24 characters .
• A customer character pattern can be programmable by mask option.
•. The special character pattern can be programmable by character generator RAM directly.
• It is possible to read both character generator and display data RAM from MPU.
• Useful 11 code instruction set
• Automatic power on reset function
• On chip generation of LCD supply voltage from voltage doubler ( external supply also possible )
•.Voltage doubler generates about double from single power supply ( 5V)
• High contrast display can be performed though the simple power supply circuits.
• On chip oscillator requires external resistor ( external clock also possible )
• Power supply voltage: +5V10%, +3V20%
• Supply voltage for display: -5V
• Package outline: 118 TAB or bare chip available.
KS0071B
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
Busy
flag
Parallel/ serial data
Conversion circuit
55
Character
generator
ROM
(CG ROM)
9600 bits
Character
generator
RAM
(CG RAM)
512 bits
60 bit
shift register
Cursor
blink
control
circuit
60
DB0~DB3
4
DB4~DB7
4
Input
output
buffer
8
R/W
RS
E
8
VDD
VDD
V1 V1
V2 V2
V3 V3
V4 V4
V5 V5
VSS
VSS
Data
register
(DR)
7
Instruction
register
(IR)
Voltage
doubler
88
7
78
Display
data RAM
(DD RAM)
640 bits
8 Instruction
decoder
7
Address
counter
Timing
generation
circuit
RC
oscillator
60
60 bit
latch
circuit
60
Segment
signal
60
driver
Segment Signal
( S1 ~ S60 )
32 bit
shift
register
32
Common
signal
driver
32
Common Signal
( C1 ~ C32 )
VCI C1 C2 V5OUT
OSC1 OSC2
T1 T2
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