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Número de pieza | PYA28HC256 | |
Descripción | STATIC CMOS RAM | |
Fabricantes | PYRAMID | |
Logotipo | ||
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No Preview Available ! FEATURES
Access Times of 70, 90 and 120ns
Single 5V±10% Power Supply
Simple Byte and Page Write
Low Power CMOS:
- 80 mA Active Current
- 3 mA Standby Current
Fast Write Cycle Times
PYA28HC256
HIGH SPEED 32K x 8 EEPROM
Software Data Protection
CMOS & TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Data Retention: 10 Years
Available in the following package:
– 28-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
DESCRIPTION
The PYA28HC256 is a 5 Volt 32Kx8 EEPROM. The device
supports 64-byte page write operation. The PYA28HC256
features DATA and Toggle Bit Polling as well as a system
software scheme used to indicate early completion of a
Write Cycle. The device also includes user-optional soft-
ware data protection. Data Retention is 10 Years. The
device is available in a 28-Pin 600 mil wide Ceramic DIP
and 32-Pin LCC.
Functional Block Diagram
Pin Configuration
Document # EEPROM106 REV 03
DIP (C5-1)
LCC (L6)
Revised October 2014
1 page POWER-UP TIMING
Symbol
Parameter
tPUR Power-up to Read operation
tPUW Power-up to Write operation
PYA28HC256 - HIGH SPEED 32K x 8 EEPROM
Max Unit
100 µs
5 ms
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym Parameter
-70
Min Max
tAVAV
tAVQV
tELQV
tOLQV
tELQX
tEHQZ
tOLQX
tOHQZ
tAVQX
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Chip Disable to to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold from Address Change
70
70
70
35
0
35
0
35
0
-90
Min Max
90
90
90
40
0
40
0
40
0
-120
Min Max
120
120
120
50
0
50
0
50
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF READ CYCLE
Document # EEPROM106 REV 03
Page 5
5 Page PYA28HC256 - HIGH SPEED 32K x 8 EEPROM
APPLICATION NOTE - SOFTWARE CHIP ERASE
The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of
6-byte load commands to specific address locations with specific data patterns. Once the code has been entered, the
device will set each byte to the high state (FFH). After the software chip erase has been initiated, the device will inter-
nally time the erase operation so that no external clocks are required. The maximum time required to erase the whole
chip is tEC (20 ms). The software data protection is still enabled even after the software chip erase is performed.
CHIP ERASE CYCLE CHARACTERISTICS
Symbol Parameter
tEC Chip Erase Cycle Time
20 ms Max
CHIP ERASE SOFTWARE ALGORITHM(1)(3)
Notes:
1. Data Format: (Hex); Address Format: (Hex).
2. After loading the 6-byte code, no byte loads are allowed
until the completion of the erase cycle. The erase cycle
will time itself to completion in 20 ms (max).
3. The flow diagram shown is for a x8 part. For a x16 part,
the data should be 16 bits long (e.g., the data to be
loaded should be AAAA for step 1 in the algorithm).
CHIP ERASE CYCLE WAVEFORMS
Notes:
1. OE must be high only when WE and CE are both low.
Document # EEPROM106 REV 03
Page 11
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet PYA28HC256.PDF ] |
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