NB3N3020 반도체 회로 부품 판매점
LVPECL/LVCMOS Clock Multiplier
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 ON Semiconductor |
NB3N3020
3.3 V, LVPECL/LVCMOS
Clock Multiplier
Description
The NB3N3020 is a high precision, low phase noise selectable clock
multiplier. The device takes a 5 – 27 MHz fundamental mode parallel
resonant crystal or a 2 − 210 MHz LVCMOS single ended clock source
and generates a differential LVPECL output and a single ended
LVCMOS/LVTTL output at a selectable clock output frequency which
is a multiple of the input clock frequency. Three tri−level (Low, Mid,
High) LVCMOS/LVTTL single ended select pins set one of 26
possible clock multipliers. The LVCMOS/LVTTL output enable
(OE1) tri−states the LVCMOS/LVTTL clock output (CLK1) when
low. When the LVTTL/LVCMOS output enable (OE2) is LOW,
LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.
This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin
package.
Features
• Selectable Clock Multiplier
• External Loop Filter is Not Required
• LVPECL Differential Output
• LVCMOS/ LVTTL Outputs
• RMS Period Jitter of 5 ps
• Jitter or Low Phase Noise at 125 MHz [25 MHz Input]:
Offset
Noise Power
100 Hz
−95 dBc/Hz
1 kHz
−107 dBc/Hz
10 kHz
−112 dBc/Hz
100 kHz
−117 dBc/Hz
1 MHz
−117 dBc/Hz
10 MHz
−134 dBc/Hz
• Operating Range 3.3 V ±10%
• Industrial Temperature Range −40°C to +85°C
• These are Pb−Free Devices
http://onsemi.com
16
1
TSSOP−16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
3020
ALYWG
1G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(*Note: Microdot may be in either location)
VDD
X1/CLK
X2
Sel2
Sel1
Sel0
OE1
GND
PIN CONFIGURATION
1 16
(Top View)
OE2
VDD
CLK2
CLK2
GND
VDD
CLK1
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 4
1
Publication Order Number:
NB3N3020/D
5−27 MHz Crystal
or
2 – 210 MHz Clock
X1 / CLK
X2
NB3N3020
VDD
GND
OE2
Clock
Buffer/
Crystal
Oscillator
Pre
Slecra
Phase
Detector
Loop Filter
VCO
%N
Select Control Block
Sel0 Sel1 Sel2
Figure 1. NB3N3020 Simplified Logic Diagram
LVPECL
Output
LVCMOS/
LVTTL
Output
CLK2
CLK2
CLK1
OE1
Table 1. PIN DESCRIPTION
Pin Name
I/O
6
Sel0
Tri−Level Input
5
Sel1
Tri−Level Input
4
Sel2
Tri−Level Input
1, 11, 15
2
VDD
X1/CLK
Power Supply
Input
3 X2
Input
7
16
8, 9, 12
13
14
10
OE1
OE2
GND
CLK2
CLK2
CLK1
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
Power Supply
LVPECL Output
LVPECL Output
LVTTL/ LVCMOS
Output
Description
Frequency select input 0. When left open, defaults to VDD/ 2. See output select Table 2
for details.
Frequency select input 1. When left open, defaults to VDD/ 2. See output select Table 2
for details.
Frequency select input 2. When left open, defaults to VDD/ 2. See output select Table 2
for details.
Positive supply voltage pins are connected to +3.3 V supply voltage.
Crystal or Clock input. Connect to 5 − 27 MHz crystal source or 2 – 210 MHz single−
ended clock. See Table 2.
Crystal input. Connect to a 5 – 27 MHz crystal or leave unconnected for clock input. See
Table 2.
Output enable input that synchronously tri−states CLK1 output when low. Internal pull−up
resistor to VDD.
Output enable input that when LOW synchronously controls LVPECL outputs by forcing
CLK2 LOW and CLK2 HIGH. Internal pull−up resistor to VDD.
Ground 0 V. These pins provide GND return path for the devices.
Inverted clock output. Clock frequency equals input frequency times multiplier.
Non−inverted clock output. Clock frequency equals input frequency times multiplier.
Clock Output. Clock frequency equals input frequency times multiplier.
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NB3N3020 cmos
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[ NB3N3020.PDF ]
[ NB3N3020 다른 제조사 검색 ]
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상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
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