74LVX373 반도체 회로 부품 판매점
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
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 STMicroelectronics |
74LVX373
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s HIGH SPEED:
tPD=5.8ns (TYP.) at VCC = 3.3V
s 5V TOLERANT INPUTS
s POWER-DOWN PROTECTION ON INPUTS
s INPUT VOLTAGE LEVEL:
)VIL = 0.8V, VIH = 2V at VCC =3V
t(ss LOW POWER DISSIPATION:
cICC = 4 µA (MAX.) at TA=25°C
us LOW NOISE:
dVOLP = 0.3V (TYP.) at VCC =3.3V
ros SYMMETRICAL OUTPUT IMPEDANCE:
P|IOH| = IOL = 4 mA (MIN) at VCC =3V
s BALANCED PROPAGATION DELAYS:
tetPLH ≅ tPHL
les OPERATING VOLTAGE RANGE:
oVCC(OPR) = 2V to 3.6V (1.2V Data Retention)
bss PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
- Os IMPROVED LATCH-UP IMMUNITY
t(s)DESCRIPTION
The 74LVX373 is a low voltage CMOS OCTAL
cD-TYPE LATCH with 3 STATE OUTPUT NON
duINVERTING fabricated with sub-micron silicon
rogate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
Poperated and low noise 3.3V applications.
teThis 8 bit D-Type latch is controlled by a latch
leenable input (LE) and an output enable input (OE).
oWhile the LE input is held at a high level, the Q
soutputs will follow the data input precisely.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX373MTR
74LVX373TTR
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
ObFigure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 4
1/13
74LVX373
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL NAME AND FUNCTION
1 OE 3 State Output Enable
Input (Active LOW)
3, 4, 7, 8, 13, D0 to D7 Data Inputs
14, 17, 18
2, 5, 6, 9, 12, Q0 to Q7 3-State Outputs
15, 16,19
11 LE Latch Enable Input
10 GND Ground (0V)
20 VCC Positive Supply Voltage
t(s)Table 3: Truth Table
ucINPUTS
rodOE LE
HX
PL L
teL H
leL H
soX : Don’t Care
bZ : High Impedance
* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level
Obsolete Product(s) - OFigure 3: Logic Diagram
D
X
X
L
H
OUTPUT
Q
Z
NO CHANGE*
L
H
This logic diagram has not be used to estimate propagation delays
2/13
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( stm )
74LVX373 cmos
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
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