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PDF MX25V512E Data sheet ( Hoja de datos )

Número de pieza MX25V512E
Descripción 512K-BIT [x 1/x 2] CMOS SERIAL FLASH
Fabricantes MACRONIX 
Logotipo MACRONIX Logotipo



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MX25V512E
MX25V512E
DATASHEET
P/N: PM1734
REV. 1.3, NOV. 13, 2013
1
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1 page




MX25V512E pdf
HARDWARE FEATURES
SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Output for Dual output mode
• SO/SIO1
- Serial Data Output or Serial Data Output for Dual output mode
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-USON (2x3mm)
- 8-pin TSSOP (173mil)
- 8-pin SOP (150mil)
- All devices are RoHS compliant and Halogen-free
MX25V512E
GENERAL DESCRIPTION
MX25V512E is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25V512E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
MX25V512E provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and
erase command is executed on chip or sector (4K-bytes).
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via the WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 25uA DC cur-
rent.
The MX25V512E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM1734
REV. 1.3, NOV. 13, 2013
5
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5 Page





MX25V512E arduino
MX25V512E
Table 3. Memory Organization
Sector
15
:
3
2
1
0
Address Range
00F000h
00FFFFh
::
003000h
003FFFh
002000h
002FFFh
001000h
001FFFh
000000h
000FFFh
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure the device is ready for the intended
operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to fol-
low tCHCL spec. (Please refer to Table 6. AC CHARACTERISTICS)
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge. The CS# rising time needs to follow tCLCH spec. (Please refer to Table 6. AC CHARACTERISTICS)
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of
SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 2.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, DREAD, RES and REMS the shifted-in in-
struction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be
high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high
exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is ne-
glected and will not affect the current operation of Write Status Register, Program, and Erase.
Figure 2. Serial Modes Supported
CPOL CPHA
(Serial mode 0) 0
0 SCLK
shift in
shift out
(Serial mode 3) 1
1 SCLK
SI
MSB
SO MSB
Note: CPOL indicates clock polarity of Serial master:
-CPOL=1 for SCLK high while idle,
-CPOL=0 for SCLK low while not transmitting.
CPHA indicates clock phase.
The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
P/N: PM1734
11
REV. 1.3, NOV. 13, 2013
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