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Integrated Circuit Systems |
Integrated
Circuit
Systems, Inc.
ICS83021I
1-TO-1
2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
GENERAL DESCRIPTION
The ICS83021I is a 1-to-1 Differential-to-
ICS LVCMOS/LVTTL Translator and a member of
HiPerClockS™ t h e H i Pe r C l o ckS™fa m i l y of H i g h Pe r fo r -
mance Clock Solutions from ICS. The differ-
ential input is highly flexible and can accept the
following input types: LVPECL, LVDS, LVHSTL, SSTL, and
HCSL. The small 8-lead SOIC footprint makes this device
ideal for use in applications with limited board space.
www.DataSheet4U.com
FEATURES
• One LVCMOS / LVTTL output
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 350MHz (typical)
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.21ps (typical), 3.3V output
• Small 8 lead SOIC package saves board space
• Full 3.3V, 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK
nCLK
Q0
PIN ASSIGNMENT
nc
CLK
nCLK
nc
1
2
3
4
8 VDD
7 Q0
6 nc
5 GND
ICS83021I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
83021AMI
www.icst.com/products/hiperclocks.html
1
REV. C DECEMBER 12, 2005
Integrated
Circuit
Systems, Inc.
ICS83021I
1-TO-1
2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 4, 6
nc Unused
No connect.
2
CLK
Input Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup Inverting differential clock input.
5
GND
Power
Power supply ground.
7 Q0 Output
Single clock output. LVCMOS / LVTTL interface levels.
www.DataSheet4U.com8
VDD Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
RPULLUP
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD = 3.6V
Minimum
5
Typical
4
23
51
51
7
Maximum Units
pF
pF
kΩ
kΩ
12 Ω
83021AMI
www.icst.com/products/hiperclocks.html
2
REV. C DECEMBER 12, 2005
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