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74VCXH16374 반도체 회로 부품 판매점

LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP



ST Microelectronics 로고
ST Microelectronics
74VCXH16374 데이터시트, 핀배열, 회로
www.DataSheet4U.com
74VCXH16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s 3.6V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED :
tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V
tPD = 3.9 ns (MAX.) at VCC = 2.3 to 2.7V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3.0V
|IOH| = IOL = 18mA (MIN) at VCC = 2.3V
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.3V to 3.6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H16374
s BUS HOLD PROVIDED ON DATA INPUTS
s LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74VCXH16374 is a low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C2MOS
technology. It is ideal for low power and very high
speed 2.3 to 3.6V applications; it can be interfaced
to 3.6V signal environment for both inputs and
outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable
inputs (nOE).
On the positive transition of the (nCK), the nQ
outputs will be set to the logic state that were
setup at the nD inputs.
While the (nOE) input is low, the 8 outputs (nQ)
will be in a normal state (HIGH or LOW logic level)
and while high level the outputs will be in a high
impedance state.
Any output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Bus hold on data inputs is provided in order to
eliminate the need for external pull-up or
pull-down resistor.
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74VCXH16374TTR
February 2003
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74VCXH16374 데이터시트, 핀배열, 회로
74VCXH16374
All inputs and outputs are equipped with
protection circuits against static discharge, giving
INPUT AND OUTPUT EQUIVALENT CIRCUIT
them 2KV ESD immunity and transient excess
voltage.
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1 1OE 3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs
11, 12
13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs
19, 20, 22, 23
24 2OE 3 State Output Enable
Input (Active LOW)
25 2CK Clock Input
36, 35, 33, 32, 2D0 to 2D7 Data Inputs
30, 29, 27, 26
47, 46, 44, 43, 1D0 to 1D7 Data Inputs
41, 40, 38, 37
48 1CK Clock Input
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
VCC Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUT
OE CK
HX
L
DQ
XZ
X NO CHANGE*
L LL
L HH
X : Don‘t Care
Z : High Impedance
IEC LOGIC SYMBOLS
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74VCXH16374 cmos

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