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PDF IN24LC04B Data sheet ( Hoja de datos )
| Número de pieza | IN24LC04B | |
| Descripción | (IN24LC04B / IN24LC08B) 4K/8K 2.5V CMOS Serial EEPROMs | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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m TECHNICAL DATA
t4U.co IN24LC04B/08B
4K/8tKaS2h.5eVe CMOS Serial EEPROMsDESCRIPTION
aIN24LC04B/08B is a 4K-or 8K-bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x
.D8 bit memory with a two wire serial interface. Low voltage design permits operation down to 2.5 volts with standby and
wactive currents of only 5µA and 1mA respectively. The IN24LC04B/08B also has a page-write capability for up to 16
wwbytes of data. The IN24LC04B/08B is available in the standard 8-pin DIP.
FEATURES
m• Single supply with operation down to 2.5V
o• Low power CMOS technology
.c- 1 mA active current typical
- 10 µA standby current typical at 5.5V
U- 5 µA standby current typical at 3.0V
t4• Organized as two or four blocks of 256 bytes (2x256x8) and
(4x256x8)
e• Two wire serial interface bus, I2C compatible
e• Schmitt trigger, filtered inputs for noise suppression
h• Output slope control to eliminate ground bounce
S• 100 kHz (2.5V) and 400 kHz (5V) compatibility
ta• Self-timed write cycle (including auto-erase)
a• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
.D• Hardware write protect for entire memory
• Can be operated as a serial ROM
w• Factory programming (QTP) available
w• ESD protection > 4,000V
w• 1,000,000 ERASE/WRITE cycles guaranteed*
m• Data retention > 200 years
.co• 8-pin DIP
t4U• Temperature range -40 to +85 oC
PACKAGE
TA = -40 ... +85 °C
Name
PINNING
Function
Vss Ground
SDA
Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
VCC
+2.5V to 5.5V Power Supply
AO, A1, A2 No Internal Connection
Pin Connection
A0 1
A1 2
8 Vcc
7 WP
eeA2 3
6 SCL
www.DataShVss 4
5 SDA
1
1 page  
IN24LC04B/08B
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
Note: The IN24LC04B/08B does not generate any acknowledge bits if an internal programming cycle is in
progress
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse
in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the data line HIGH to enable the master to
generate the STOP condition.
Figure 4. Data Transfer Sequence on the serial bus
BUS CHARACTERISTICS
Device Addressing and Operation
A control byte is the first byte received following the start condition from the master device. The
control byte consists of a four bit control code, for the IN24LC04B/08B this is set as 1010 binary
for read and write operations. The next three bits of the control byte are the block select bits (B2,
B1, BO). B2 is a don't care for both the IN24LC04B and IN24LC08B; B1 is a don't care for the
IN24LC04B. They are used by the master device to select which of the two or four 256 word blocks
of memory are to be accessed. These bits are in effect the most significant bits of the word address.
The last bit of the control byte defines the operation to be performed. When set to one a read
operation is selected, when set to zero a write operation is selected. Following the start condition,
the IN24LC04B/08B monitors the SDA bus checking the device type identifier being transmitted,
upon a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the IN24LC04B/ 08B will select a read or write operation.
Operation
Read
Write
Control Code
1010
1010
Block Select
Block Address
Block Address
R/W
1
0
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IN24LC04B.PDF ] | |
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