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OV5116N
OV5116N SINGLE IC CMOS MONOCHROME CAMERA WITH NTSC ANALOG OUTPUT
Features
Single chip 1/4 inch format video image sensor
EIA/NTSC output
Selectable mirror image
Auto gain control (maximum + 18 dB)
High I.R. sensitivity for nighttime applications
Auto and manual backlight compensation mode
Gamma correction -On/Off
General Description
The OV5116N is a complete black and white CMOS Video
Camera chip. It conforms to EIA/NTSC (60 Hz) standards
and outputs composite video capable of directly driving a 75Ω
display device.
The on-chip auto exposure allows for a wide range of lighting
conditions, eliminating the need for external mechanical shut-
ter components. This, along with its single supply, low power
consumption makes the OV5116N an incredibly versatile and
cost-effective video camera perfect for the following types of
applications:
External frame sync capability
40mw on-chip power consumption
External data acquisition support
Smear free
Auto level expanding
Optional edge enhancement
Applications
Security
Surveillance
Machine Vision
Process Control
CCTV
Infant Monitoring
Toys
4 3 2 1 28 27 26
ABOFF 5
VCBRT 6
SGND 7
NTSC 8
BKLT 9
XTAL2 10
XTAL1 11
OV5116N
28 PIN LCC
25 DEGND
24 ATBLKT
23 OVDD
22 CVO
21 DGND
20 DVDD
19 PCLK/G8X
12 13 14 15 16 17 18
Key Specifications
Array Size
320 x 240 pixels
Effective Image
Area
3.2 x 2.5mm
Auto Electronic
Exposure
(seconds)
1/60-1/6000
Minimum
Illumination
0.5 lux @ f 1.4
(3000k)
S/N Ratio
46 dB (AGC=1x)
Power Supply
5VDC, ±5%
Power
Requirements
(40 mw before-
loading), 70mw
standard loading
Package Type
28 pin LCC
OV5116N PIN ASSIGNMENT
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A.
Tel: (408) 733-3030 Fax: (408) 733-3061
e-mail: [email protected]
Website: http://www.ovt.com
Version 2.1, May 4, 2001
OMNIVISION TECHNOLOGIES, Inc.
OV5116N
SINGLE IC CMOS MONOCHROME CAMERA WITH NTSC ANALOG OUTPUT
1. Introduction
This section describes the features and functions of the OV5116N, a monochrome CMOS video camera integrated circuit.
2. Pin Assignments:
Table 1. Pin Descriptions
Pin #
Name
Class
Function
1, 2, 20,
23, 26
AVDD, SVDD,
DVDD, OVDD
DEVDD
Bias
Power (+5V) connections.
3 VRCHG
OA Internal voltage reference. Connect to AGND with a 0.1uF capacitor.
4 N50
I-Ø Set low(Ø)=standard NTSC. Set high (1)=50hz light (For use in Japan Only);
5 ABOFF
I-Ø Auto brightness level descending function off
6 VCBRT
OA Video DC Output Black level, leave it open in usual case
7, 21,
25, 28
SGND, DGND,
DEGND, AGND
Bias Ground connections. Connect to supply common.
8 NTSC
I-1 Set high(1)=EIA/NTSC mode
*9 BKLT
I-Ø Backlight mode 1
10 XTAL2
XO Oscillator clock output or crystal output.
11 XTAL1
XI External oscillator input or crystal input: 12.288MHz
12 FSI
I-Ø External frame sync input. A rising edge on FSI sets the chip timing to vertical sync.
Leave open if unused.
13 OENB
I-Ø A logic level input to enable or tri-state CVO. Logic high(1)=tri-state;low(Ø)=enabled.
14 G4X
I-Ø A logic level input which when high places the maximum AGC gain to 4x. When low the
sensor AGC gain is 2x.
15 FAST
I-Ø A logic level input to enable/disable AGC/AEC FAST mode. High enables, low disables,
which provides slow and smooth AGC/AEC mode.
16 BPED
I-Ø A logic level input to disable on chip edge enhancement. High disable, low enable.
17 GAMMA
I-1 A logic level pin to select the transfer characteristic of output voltage versus light input.
Logic high for g=0.45; low for g=1.
18 FSO/MIRR
I/O In/out pin.Frame Sync Output. Digital frame sync output pin. Positive pulse occurs during
Ø/Ø
the CVO vertical sync period. Input is a logic level input to enable mirror function.
Low(Ø)=Standard, High(1)=Mirror.
19 PCLK/G8X
I/O Digital pixel clock output. Provides 2 functions: When high a valid pixel is present at CVO
Ø/Ø
and in sync with PCLK. Input is a logic level input to enable maximum AGC gain to 8x
(only effective when pin 14 is set to high(1))
22 CVO
Q The composite video output signal. The output is a source follower capable of directly
driving a 1V p-p signal into a 108 Ω load.(75Ω external and 33Ω internal)
*24 ATBLKT
I-Ø Backlight mode 2
27 VREQ
OA Internal voltage reference level. Connect to AGND with a 0.1uF capacitor.
* Pin 9 and Pin 24 must be used in a logical combination as per the following table:
ATBLK(Pin 24)
Ø
Ø
1
1
BLKT(Pin 9)
Ø
1
Ø
1
Mode
Normal Mode
Mode 1 - Manual Back light
Mode 2 – Automatic Back light (Chip determination)
Future Use
Class
Default Level
I-1 digital input, with 100k pull up
I-Ø digital input, with 100k pull down
I/O digital CMOS level input and output
OA analog CMOS reference voltage
Q 75 ohm output
XI/XO
crystal input/output
Bias
power supply bias
Ø: Low; O: Output
May 4, 2001
Version 2.1
2
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