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28C256 반도체 회로 부품 판매점

256K 32K x 8 Paged CMOS E2PROM



ATMEL Corporation 로고
ATMEL Corporation
28C256 데이터시트, 핀배열, 회로
AT28C256
Features
Fast Read Access Time - 150 ns
•• Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 3 ms or 10 ms Maximum
1 to 64-Byte Page Write Operation
Low Power Dissipation
50 mA Active Current
200 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
•• High Reliability CMOS Technology
Endurance: 104 or 105 Cycles
Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
•• Full Military, Commercial, and Industrial Temperature Ranges
256K (32K x 8)
Paged
CMOS
E2PROM
Description
The AT28C256 is a high-performance Electrically Erasable and Programmable Read
Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access
times to 150 ns with power dissipation of just 440 mW. When the device is deselected,
the CMOS standby current is less than 200 µA.
(continued)
Pin Configurations
Pin Name
A0 - A14
CE
OE
WE
I/O0 - I/O7
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
Don’t Connect
TSOP
Top View
PGA
Top View
LCC, PLCC
Top View
CERDIP, PDIP,
FLATPACK, SOIC
Top View
AT28C256
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
0006F
2-217


28C256 데이터시트, 핀배열, 회로
Description (Continued)
The AT28C256 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writ-
ing of up to 64-bytes simultaneously. During a write cycle,
the addresses and 1 to 64-bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
Atmel’s 28C256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inad-
vertent writes. The device also includes an extra 64-bytes
of E2PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2-218 AT28C256




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제조업체: ATMEL Corporation

( atmel )

28C256 cmos

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