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PDF NM27C210 Data sheet ( Hoja de datos )
| Número de pieza | NM27C210 | |
| Descripción | 1 /048 /576-Bit (64K x 16) High Performance CMOS EPROM | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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July 1998
NM27C210
1,048,576-Bit (64K x 16) High Performance
CMOS EPROM
General Description
The NM27C210 is a high performance Electrically Programmable
UV erasable ROM (EPROM). It contains 1,048,576 bits config-
ured as 64K x 16 bit. It is offered in both erasable versions for
prototyping and early production applications as well as non-
erasable, plastic packaged versions that are ideal for high volume
and automated assembly applications.
The NM27C210 operates from a single 5 volt ±10% supply in the
read mode.
The NM27C210 is offered in both DIP and surface mount pack-
ages. The DIP package is a 40-pin dual-in-line ceramic with a
quartz window to allow erasing. The surface mount package is a
44-pin PLCC that is offered in OTP.
This EPROM is manufactured using Fairchild’s proprietary AMG™
EPROM technology for an excellent combination of speed and
economy while providing excellent reliability.
Features
s High performance CMOS
— 90 ns access time
s Fast turn-off for microprocessor compatibility
s Simplified upgrade path
—VPP and PGM are “Don’t Care” during normal read
operation
s Compatible with 27210 and 27C210 EPROMs
s Manufacturer’s identification code
s Fast programming
s JEDEC standard pin configuration
— 40-pin CDIP package
— 40-pin PDIP package
— 44-pin PLCC package
Block Diagram
Vcc
GND
Vpp
OE
PGM
CE
A0 - A15
Address
Inputs
Output Enable
Chip Enable, and
Program Logic
Y
Decoder
X
Decoder
Data Outputs O0 - O15
Output
Buffers
4,194,304-Bit
Cell Matrix
DS011093-1
AMG™ is a trademark of WSI, Inc.
© 1998 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
1 page  
Programming Characteristics (Note 11), (Note 12), (Note 13), (Note 14), and (Note 15)
Symbol
tAS
tOES
tCES
tDS
tVPS
tVCS
tAH
tDH
tDF
tPW
tOE
IPP
ICC
TA
VCC
VPP
tFR
VIL
VIH
tIN
tOUT
Parameter
Address Setup Time
OE Setup Time
CE Setup Time
Data Setup Time
VPP Setup Time
VCC Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
Program Pulse Width
Data Valid from OE
VPP Supply Current during
Programming Pulse
VCC Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
OE = VIH
CE = VIL
CE = VIL
CE = VIL
PGM = VIL
Min
1
1
1
1
1
1
0
1
0
45
20
6.25
12.5
5
2.4
0.8
0.8
Typ
50
25
6.5
12.75
0.0
4.0
Max
60
105
100
40
50
30
6.75
13.0
0.45
2.0
2.0
Units
µs
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
mA
mA
°C
V
V
ns
V
V
V
V
Programming Waveforms (Note 13)
Program
Adresses
2.0V
0.8V
Address N
Data
2.0V
0.8V
tAS
Data In Stable
Add N
High Z
6.25V
VCC
tDS
tVCS
tDH
Program Verify
tAH
Data Out Valid
Add N
tDF
VPP 12.75V
tVPS
CE/PGM
2.0V
0.8V
tPW tOES tOE
OE
2.0V
0.8V
DS011093-5
Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14: Programming and program verify are tested with the turbo Program Algorithm, at typical power supply voltages and timings.
Note 15: During power up the PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.
5 www.fairchildsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NM27C210.PDF ] | |
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