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PDF 8102406VA Data sheet ( Hoja de datos )
| Número de pieza | 8102406VA | |
| Descripción | 1024 x 4 CMOS RAM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HM-6514
March 1997
1024 x 4 CMOS RAM
Features
Description
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device utilizes
synchronous circuitry to achieve high performance and low
power operation.
• TTL Compatible Input/Output
• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
On-chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6514 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
HM3-6514S-9
HM1-6514S-9
24502BVA
8102402VA
-
-
200ns
HM3-6514B-9
HM1-6514B-9
-
8102404VA
-
-
300ns
HM3-6514-9
HM1-6514-9
-
8102406VA
-
HM4-6514-B
TEMPERATURE RANGE
-40oC to +85oC
-40oC to +85oC
-
-
-40oC to +85oC
-55oC to +125oC
PACKAGE
PDIP
CERDIP
JAN#
SMD#
CLCC
PKG. NO.
E18.3
F18.3
F18.3
F18.3
J18.B
J18.B
Pinouts
HM-6514 (PDIP, CERDIP)
TOP VIEW
A6 1
A5 2
A4 3
A3 4
A0 5
A1 6
A2 7
E8
GND 9
18 VCC
17 A7
16 A8
15 A9
14 DQ0
13 DQ1
12 DQ2
11 DQ3
10 W
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
Q Data Output
HM-6514 (CLCC)
TOP VIEW
2 1 18 17
A4 3
16 A8
A3 4
15 A9
A0 5
14 DQ0
A1 6
13 DQ1
A2 7
12 DQ2
8 9 10 11
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 2995.1
1 page  
HM-6514
Timing Waveforms
(2) TAVQV
(7)
TAVEL
(8)
TELAX
A VALID ADD
(6)
TEHEL
(2) TAVQY
E
HIGH Z
DQ
(1) TELQV
(3) TELQX
(17) TELEL
(5) TELEH
(7) TAVEL
NEXT ADD
(6)
TEHEL
(4) TEHQZ
VALID DATA OUT
HIGH Z
W
TIME
REFERENCE
TIME
REFERENCE
-1
0
1
2
3
4
5
-1 0
INPUTS
EW
HX
H
LH
LH
H
HX
H
1
FIGURE 1. READ CYCLE
TRUTH TABLE
2
34
5
DATA I/O
A DQ
FUNCTION
X Z Memory Disabled
V Z Cycle Begins, Addresses are Latched
X X Output Enabled
X V Output Valid
X V Read Accomplished
X Z Prepare for Next Cycle (Same as -1)
V Z Cycle Ends, Next Cycle Begins (Same as 0)
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled, but data is not valid until during time (T = 2). W
must remain high throughout the read cycle. After the output
data has been read, E may return high (T = 3). This will dis-
able the output buffer and all inputs, and ready the RAM for
the next memory cycle (T = 4).
6-5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 8102406VA.PDF ] | |
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