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VG36256801A 반도체 회로 부품 판매점

CMOS Synchronous Dynamic RAM



Vanguard International Semiconductor 로고
Vanguard International Semiconductor
VG36256801A 데이터시트, 핀배열, 회로
VIS
Description
Preliminary
VG36256401A
VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 16,777,216 - word x 4 -bit x 4 - bank,
8,388,608 - word x 8 - bit x 4 - bank, or 4,194,304 - word x 16 - bit x 4 - bank. These various organizations
provide wide choice for different applications. It is designed with the state-of-the-art technology to meet stan-
dard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the perfor-
mance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
• Single 3.3V ( ±0.3V) power supply
• High speed clock cycle time : 7.5ns/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A13 & A14 (Bank select)
• Each Banks can operate simultaneously and independently
• I/O level : LVTTL compatible
• Random column access in every cycle
• x4, x8, x16 organization
• Input/Output controlled by DQM, LDQM, UDQM
• 8,192 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0155
Rev.1
Page 1


VG36256801A 데이터시트, 핀배열, 회로
VIS
Pin Configuration
Preliminary
VG36256401A
VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
VDD
DQ0
VDDQ
DQ1
VDD
DQ0
VDDQ
NC
VDD
NC
VDDQ
NC
DQ2
VSSQ
DQ3
DQ1
VSSQ
NC
DQ0
VSSQ
NC
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDD
NC
WE WE WE
CAS
CAS
CAS
RAS
RAS
RAS
CS CS CS
A14/(BA0) A14/(BA0) A14/(BA0)
A13/(BA1) A13/(BA1) A13/(BA1)
A10/AP
A0
A1
A2
A3
VDD
A10/AP
A0
A1
A2
A3
VDD
A10/AP
A0
A1
A2
A3
VDD
VG36256161 X 16
VG36256801 X 8
VG36256401 X 4
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
VSS
VSS
VSS
NC DQ7 DQ15
VSSQ
VSSQ
VSSQ
NC
DQ3
VDDQ
NC
NC
DQ6
VDDQ
NC
DQ14
DQ13
VDDQ
DQ12
NC
VSSQ
DQ5
VSSQ
DQ11
VSSQ
NC NC DQ10
DQ2
VDDQ
NC
VSS
NC,VREF
DQ4
VDDQ
NC
VSS
NC,VREF
DQ9
VDDQ
DQ8
VSS
NC,VREF
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Description
VG36256401/VG36256801/VG36256161
Pin Name
Function
A0 - A12
A13, A14
Address inputs
Bank select
DQ0 ~ DQ15
RAS
CAS
WE
VSS
VDD
Data - in/data - out
Row address strobe
Column address strobe
Write enable
Ground
Power (+ 3.3V)
Pin Name
DQM,
LDQM,
UDQM,
CLK
CKE
CS
VDDQ
VSSQ
Function
Upper DQ Mask enable,
Lower DQ Mask enable
Clock input
Clock enable
Chip select
Supply voltage for DQ
Ground for DQ
Document : 1G5-0155
Rev.1
Page 2




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