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VG3617161BT 반도체 회로 부품 판매점

16Mb CMOS Synchronous Dynamic RAM



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VG3617161BT 데이터시트, 핀배열, 회로
VIS
VG3617161BT
16Mb CMOS Synchronous Dynamic RAM
Description
The VG3617161BT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
power supply. This SDRAM is delicately designed with performance concern for current high-speed applica-
tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It
is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
• Single 3.3V +/- 0.3V power supply
• Clock Frequency: 200MHz, 183MHz, 166MHz, 143MHz, 125MHz
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual internal banks controlled by A11(Bank select)
• Simultaneous and independent two bank operation
• I/O level : LVTTL interface
• Random column access in every cycle
• X16 organization
• Byte control by LDQM and UDQM
• 2048 refresh cycles/32ms
• Burst termination by burst stop and precharge command
Document:1G5-0150
Rev.4
Page 1


VG3617161BT 데이터시트, 핀배열, 회로
VIS
Pin Configuration
VG3617161BT
16Mb CMOS Synchronous Dynamic RAM
Pin Description
(VG3617161BT)
Pin Name
A0-A11
DQ0~DQ15
RAS
CAS
WE
VSS
VDD
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
(BS)A11
A10
A0
A1
A2
A3
VDD
50-Pin Plastic TSOP(II)(400 mil)
1 50 VSS
2 49 DQ15
3 48 DQ14
4 47 VSSQ
5 46 DQ13
6 45 DQ12
7 44 VDDQ
8 43 DQ11
9 42 DQ10
10 41 VSSQ
11 40 DQ9
12 39 DQ8
13 38 VDDQ
14 37 NC
15 36 UDQM
16 35 CLK
17 34 CKE
18 33 NC
19 32 A9
20 31 A8
21 30 A7
22 29 A6
23 28 A5
24 27 A4
25 26 VSS
Function
Address inputs
- Row address A0-A10
- Column address A0-A7
A11: Bank select
Data-in/data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Pin Name
LDQM,
UDQM
Function
Lower DQ mask enable and
Upper DQ mark enable
CLK
CKE
CS
VDDQ
VSSQ
Clock input
Clock enable
Chip select
Supply voltage for DQ
Ground for DQ
Document:1G5-0150
Rev.4
Page 2




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VG3617161BT

16Mb CMOS Synchronous Dynamic RAM - ETC