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PDF VG26VS18165C Data sheet ( Hoja de datos )
| Número de pieza | VG26VS18165C | |
| Descripción | 1/048/576 x 16 - Bit CMOS Dynamic RAM | |
| Fabricantes | Vanguard International Semiconductor | |
| Logotipo |  |
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VIS
Description
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup,
portable electronic application. A new refresh feature called “self-refresh” is supported and very slow CBR
cycles are being performed. lt is packaged in JEDEC standard 42-pin plastic SOJ.
Features
• Single 5V(±10 %) or 3.3V(±10 %) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
- Active wode : 5V version 660/605 mW (Mas)
3.3V version 432/396 mW (Mas)
- Standby mode: 5V version 1.375 mW (Mas)
3.3V version 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 1024 refresh cycle in 16 ms(Std.) or 128 ms(S-version)
• 4 refresh modes:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Document:1G5-0147
Rev.1
Page 1
1 page  
VIS
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Supply voltage relative to Vss
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
5V
3.3V
5V
3.3V
Symbol
VT
VCC
IOUT
PD
TOPT
TSTG
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Value
-1.0 to + 7.0
-0.5 to + 4.6
-1.0 to + 7.0
-0.5 to + 4.6
50
1.0
0 to + 70
-55 to + 125
Unit
V
V
mA
W
¢J
¢J
Recommended DC Operating Conditions
Parameter/Condition
Symbol
Supply Voltage
Input High Voltage, all inputs
Input Low Voltage, all inputs
VCC
VIH
VIL
5 Volt Version
3.3 Volt Version
Min Typ
4.5 5.0
Max Min Typ
5.5 3.0 3.3
Max
3.6
2.4
- VCC + 1.0
2.0
- VCC + 0.3
-1.0 -
0.8 -0.3
-
0.8
Unit
V
V
V
Capacitance
Ta = 25°C, VCC = 5V ±10 % or 3.3V ±10 %, f = 1MHz
Parameter
Symbol
Typ
Input capacitance (Address)
CI1 -
Input capacitance
(RAS , LCAS , UCAS, OE, WE)
CI2
-
Output capacitance
(Data-in, Data-out)
CI/O
-
Note: 1. Capacitance measured with effective capacitance measuring method.
2. RAS, LCAS and UCAS = VIH to disable Dout.
Max
5
7
7
Unit
pF
pF
pF
Note
1
1
1, 2
Document:1G5-0147
Rev.1
Page 5
5 Page 
VIS
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Read Cycle
Parameter
Access time from RAS
Access time from LCAS / UCAS
Access time from column address
Access time from OE
Read command setup time
Read command hold time to LCAS / UCAS
Read command hold time to RAS
Output buffer turn-off time
Output buffer turn-off time from OE
Symbol
tRAC
tCAC
tAA
tOEA
tRCS
tRCH
tRRH
tOFF
tOEZ
VG26(V)(S)18165C
-5 -6
Min Max Min Max
- 50
- 60
- 13
- 15
- 25
- 30
- 12
- 15
0
-0
-
0
-0
-
10
- 10
-
0 12
0 15
0 12
0 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
13
14, 15
15, 16
8
11, 17
17
18
18
Write Cycle
Parameter
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to LCAS / UCAS lead time
Data-in setup time
Data-in hold time
WE to Data-in delay
Symbol
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
tWED
VG26(V)(S)18165C
-5 -6
Min Max Min Max
0 -0 -
8 - 10 -
8 - 10 -
13 - 15 -
8 - 10 -
0 -0 -
8 - 10 -
10 - 10 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
8, 19
20
21
21
Read- Modify- Write Cycle
Parameter
Read-modify- write cycle time
RAS to WE delay time
LCAS / UCAS to WE dealy time
Column address to WE delay time
OE hold time from WE
Symbol
tRWC
tRWD
tCWD
tAWD
tOEH
VG26(V)(S) 18165C
-5 -6
Min Max Min Max
108 - 133 -
64 - 77 -
26 - 32 -
39 - 47 -
8 - 10 -
Unit
ns
ns
ns
ns
ns
Notes
19
19
19
Document:1G5-0147
Rev.1
Page 11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet VG26VS18165C.PDF ] | |
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