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Vanguard International Semiconductor |
VIS
Description
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup,
portable electronic application. A new refresh feature called “self-refresh” is supported and very slow CBR
cycles are being performed. lt is packaged in JEDEC standard 26/24-pin plastic SOJ.
Features
• Single 5V( ±10%) or 3.3V(+10%,-5%) only power supply
• High speed t RAC acess time: 50/60ns
• Low power dissipation
- Active wode : 5V version 660/605 mW (Mas)
3.3V version 432/396 mW (Mas)
- Standby mode: 5V version 1.375 mW (Mas)
3.3V version 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Document:1G5-0162
Rev.1
Page 1
VIS
Pin Configuration
26/24-PIN 300mil Plastic SOJ
VCC
DQ1
DQ2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
Pin Description
Pin Name
Function
A0-A10
Address inputs
- Row address
- Column address
- Refresh address
A0-A10
A0-A10
A0-A10
DQ1~DQ4
Data-in / data-out
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
OE Output enable
Vcc Power (+5 V or + 3.3V)
Vss Ground
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Document:1G5-0162
Rev.1
Page 2
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