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K6R1008C1C- 반도체 회로 부품 판매점

128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.



Samsung semiconductor 로고
Samsung semiconductor
K6R1008C1C- 데이터시트, 핀배열, 회로
PRELIMINARY
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
Document Title
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev.No.
History
Rev. 0.0
Initial release with Preliminary.
Draft Data
Aug. 5. 1998
Remark
Preliminary
Rev. 1.0
Rev. 2.0
Release to Final Data Sheet.
1.1. Delete Preliminary.
2.2. Added Data Retention Characteristics.
Add 10ns part.
Mar. 3. 1999
Final
Mar. 3. 2000
Final
Rev. 3.0
Delete 20ns speed bin
Sep. 24. 2001
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 3.0
September 2001


K6R1008C1C- 데이터시트, 핀배열, 회로
PRELIMINARY
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)
FEATURES
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
Standby (TTL) : 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating K6R1008C1C-10 : 80mA(Max.)
K6R1008C1C-12 : 75mA(Max.)
K6R1008C1C-15 : 73mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention: L-ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R1008C1C-J : 32-SOJ-400
K6R1008C1C-T : 32-TSOP2-400CF
GENERAL DESCRIPTION
The K6R1008C1C is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 131,072 words by 8 bits.
The K6R1008C1C uses 8 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNGs advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density high-speed system applications. The
K6R1008C1C is packaged in a 400mil 32-pin plastic SOJ or
TSOP2 forward.
ORDERING INFORMATION
K6R1008C1C-C10/C12/C15
K6R1008C1C-I10/I12/I15
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O1~I/O8
Data
Cont.
Pre-Charge Circuit
Memory Array
512 Rows
256x8 Columns
I/O Circuit
Column Select
CLK
Gen.
A9 A10 A11 A12 A13 A14 A15 A16
CS
WE
OE
A0 1
A1 2
A2 3
A3 4
CS 5
I/O1 6
I/O2 7
Vcc 8
Vss 9
I/O3 10
I/O4 11
WE 12
A4 13
A5 14
A6 15
A7 16
SOJ/
TSOP2
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O8
26 I/O7
25 Vss
24 Vcc
23 I/O6
22 I/O5
21 A12
20 A11
19 A10
18 A9
17 A8
PIN FUNCTION
Pin Name
A0 - A16
WE
CS
OE
I/O1 ~ I/O8
VCC
VSS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
-2-
Revision 3.0
September 2001




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