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74ALVCH162245 반도체 회로 부품 판매점

3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS AND BUS-HOLD



Integrated Device Technology 로고
Integrated Device Technology
74ALVCH162245 데이터시트, 핀배열, 회로
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
3.3V CMOS 16-BIT BUS
TRANSCIEVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH162245
.EATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE .EATURES:
• Balanced Output Drivers: ±12mA (A port)
• High Output Drivers: ±24mA (B port)
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. The ALVCH162245 is designed for asynchronous commu-
nication between data buses. The control-function implementation mini-
mizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit
transceiver. It allows data transmission from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the
device so that the buses are effectively isolated.
The ALVCH162245 has series resistors in the device out-put structure
of the “A” port which will significantly reduce line noise when used with light
loads. This driver has been designed to drive ±12mA at the designated
threshold levels. The “B” port has a ±24mA driver.
The ALVCH162245 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
.UNCTIONAL BLOCK DIAGRAM
1DIR 1
1A1 47
1A2 46
1A3 44
43
1A 4
1A5 41
1A6 40
1A7 38
1A8 37
48
1OE
2 1B1
3 1B2
5 1B3
6
1B 4
8 1B5
9 1B6
11 1B7
12 1B8
2DIR 24
2A1 36
35
2A2
2A3 33
2A4 32
2A5 30
2A6 29
2A7 27
2A8 26
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 1999 Integrated Device Technology, Inc.
1
25
2OE
13 2B1
14 2B2
16 2B3
17 2B4
19 2B5
20 2B6
22 2B7
23 2B8
APRIL 1999
DSC-4748/1


74ALVCH162245 데이터시트, 핀배열, 회로
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
PIN CON.IGURATION
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 1OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 VCC
41 1A5
40 1A6
39 GND
38 1A7
37 1A8
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
31 VCC
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5
TSTG Storage Temperature
–65 to +150
IOUT DC Output Current
–50 to +50
IIK Continuous Clamp Current,
VI < 0 or VI > VCC
±50
IOK Continuous Clamp Current, VO < 0
–50
ICC Continuous Current through each
ISS VCC or GND
±100
Unit
V
V
°C
mA
mA
mA
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT
Output Capacitance VOUT = 0V
7
9 pF
CI/O I/O Port Capacitance VIN = 0V 7 9 pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xOE
DIR
xAx(1)
Description
Output Enable Inputs (Active LOW)
Direction Control Inputs
Side A Inputs or 3-State Outputs
xBx(1)
Side B Inputs or 3-State Outputs
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
SSOP/ TSSOP/ TVSOP
TOP VIEW
.UNCTION TABLE (EACH 8-BIT SECTION)(1)
Inputs
xOE
xDIR
Outputs
L L B data to A bus
L H A data to B bus
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
X
Isolation
2




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74ALVCH162245 cmos

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