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HM-6561883 반도체 회로 부품 판매점

256 x 4 CMOS RAM



Intersil Corporation 로고
Intersil Corporation
HM-6561883 데이터시트, 핀배열, 회로
HM-6561/883
March 1997
256 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• On-Chip Address Registers
• Common Data In/Out
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high per-
formance and low power operation.
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
• Three-State Output
• Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERATURE RANGE
220ns
CERDIP
-55oC to +125oC
HM1-6561B/883
300ns
HM1-6561/883
PKG. NO.
F18.3
Pinout
HM-6561/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
E9
18 VCC
17 A4
16 W
15 S1
14 DQ3
13 DQ2
12 DQ1
11 DQ0
10 S2
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
DQ Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-117
File Number 2990.1


HM-6561883 데이터시트, 핀배열, 회로
Functional Diagram
HM-6561/883
A0
A1
A5
A6
A7
DQ0
DQ1
DQ2
DQ3
W
E
S1
S2
LATCHED
ADDRESS
REGISTER
A
A
L
5
5
A Q LATCH
LATCH
AQ
A Q LATCH
A Q LATCH
GATED
ROW
DECODER
G
A
D
LA
D
LA
D
LA
D
L
32 x 32
32 MATRIX
8888
G
GATED COLUMN
DECODER
AND DATA I / O
3
A
3
A
L LATCHED ADDRESS
REGISTER
A2 A3 A4
NOTES:
1. All lines positive logic-active high.
2. Three-state Buffers: A high output active.
3. Data Latches: L high Q = D and Q latches on falling edge of L.
4. Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
6-118




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HM-6561883 cmos

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HM-6561883

256 x 4 CMOS RAM - Intersil Corporation