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PDF HS-302RH Data sheet ( Hoja de datos )

Número de pieza HS-302RH
Descripción Radiation Hardened CMOS Dual DPST Analog Switch
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Radiation Hardened CMOS Dual DPST Analog Switch
HS-302RH, HS-302EH
Intersil’s Satellite Applications Flow™ (SAF) devices are fully
tested and guaranteed to 100kRAD Total Dose. These QML
Class T devices are processed to a standard flow intended to
meet the cost and shorter lead-time needs of large volume
satellite manufacturers, while maintaining a high level of
reliability.
The HS-302RH, HS-302EH analog switches are a monolithic
device fabricated using Radiation Hardened CMOS technology
and the Intersil dielectric isolation process for latch-up free
operation. Improved total dose hardness is obtained by layout
(thin oxide tabs extending to a channel stop) and processing
(hardened gate oxide). These switches offer low-resistance
switching performance for analog voltages up to the supply
rails. ON-resistance is low and stays reasonably constant over
the full range of operating voltage and current. ON-resistance
also stays reasonably constant when exposed to radiation,
being typically 30Ω pre-rad and 35Ω post 100kRAD(Si). These
devices provide break-before-make switching.
Specifications
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-302RH, HS-302EH
are contained in SMD# 5962-95812.
Functional Diagram
Features
• QML class T, Per MIL-PRF-38535
• Radiation performance
- Gamma dose () 1 x 105 RAD(Si)
• No latch-up, dielectrically isolated device islands
• Pin for pin compatible with Intersil HI-302 series analog
switches
• Analog signal range 15V
• Low leakage . . . . . . . . . . . . . . . . . . . . . 100nA (Max, Post Rad)
• Low RON . . . . . . . . . . . . . . . . . . . . . . . . . . 60Ω (Max, Post Rad)
• Low operating power . . . . . . . . . . . . . .100µA (Max, Post Rad)
Pin Configurations
HS1-302RH, HS1-302EH
(14 LD SBDIP), CDIP2-T14
TOP VIEW
NC 1
S3 2
D3 3
D1 4
S1 5
IN1 6
GND 7
14 V+
13 S4
12 D4
11 D2
10 S2
9 IN2
8 V-
IN N P
D
TRUTH TABLE
LOGIC
ALL SWITCHES
0 OFF
1 ON
NC
S3
D3
D1
S1
IN1
GND
HS9-302RH, HS9-302EH
(14 LD FLATPACK), CDFP3-F14
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
V+
S4
D4
D2
S2
IN2
V-
July 31, 2013
FN4603.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2013. All Rights Reserved
Intersil (and design) and Satellite Applications Flow™ (SAF) are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 page




HS-302RH pdf
HS-302RH, HS-302EH
Ceramic Metal Seal Flatpack Packages (Flatpack)
e
-A-
PIN NO. 1
ID AREA
A
A
-B- D
S1
b
E1
0.004 M H A - B S D S
0.036 M H A - B S D S
Q
A
-C-
SEATING AND
BASE PLANE
E -D-
L E2
E3 E3
c1 LEAD FINISH
L
C
-H-
BASE
METAL
(c)
b1
NOTES:
MM
(b)
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark. Alternately, a tab (dimension k) may be
used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass over-
run.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness. The maximum limits of
lead dimensions b and c or M shall be measured at the centroid of
the finished lead surfaces, when solder dip or tin plate lead finish is
applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materi-
als shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the me-
niscus) of the lead from the body. Dimension Q minimum shall be
reduced by 0.0015 inch (0.038mm) maximum when solder dip lead
finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D - 0.390 - 9.91 3
E
0.235
0.260
5.97
6.60
-
E1 - 0.290 - 7.11 3
E2 0.125 - 3.18
-
-
E3 0.030 - 0.76 - 7
e 0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
2
L
0.270
0.370
6.86
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1 0.005 - 0.13 - 6
M
-
0.0015
-
0.04
-
N 14
14 -
Rev. 0 5/18/94
5 FN4603.3
July 31, 2013

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