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AMIC Technology |
Preliminary
A426316B Series
64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
Remark
November 15, 2000 Preliminary
PRELIMINARY (November, 2000, Version 0.0)
AMIC Technology, Inc.
Preliminary
A426316B Series
64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 65,536 words X 16 bits
n Part Identification:
- A426316B
- A426316B-L (with self-refresh mode)
n High speed
- 30/35/40 ns RAS access time
- 16/18/20 ns column address access time
- 10/11/12 ns CAS access time
n Low power consumption
- Operating: 75mA (-30 max)
- Standby: 3 mA (TTL)
Pin Configuration
n SOJ
nTSOP
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 NC
25 A7
24 A6
23 A5
22 A4
21 VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
44 VSS
43 I/O15
42 I/O14
41 I/O13
40 I/O12
39 VSS
38 I/O11
37 I/O10
36 I/O9
35 I/O8
32 NC
31 LCAS
30 UCAS
29 OE
28 NC
27 A7
26 A6
25 A5
24 A4
23 VSS
n Separate CAS ( UCAS , LCAS ) for byte selection
n Self refresh mode
n 256 refresh cycles, 4 ms refresh interval
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 400mil, 40-pin SOJ
- 400mil, 40/44 TSOP type II package
n Single 5V power supply/built-in VBB generator
Pin Descriptions
Symbol
Description
A0 – A7 Address Inputs
I/O0 - I/O15 Data Input/Output
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE Write Enable
OE Output Enable
VCC
+5V Power Supply
VSS
Ground
NC No Connection
PRELIMINARY (November, 2000, Version 0.0)
1
AMIC Technology, Inc.
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