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AD7011 반도체 회로 부품 판매점

CMOS/ ADC p/4 DQPSK Baseband Transmit Port



Analog Devices 로고
Analog Devices
AD7011 데이터시트, 핀배열, 회로
a
FEATURES
Single +5 V Supply
On-Chip /4 DQPSK Modulator
Modulator Bypass Analog Mode
Root-Raised Cosine Tx Filters, = 0.35
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Dual Mode Operation, Analog and Digital
Very Low Power Dissipation, 30 mW typical
Power Down Mode < 10 A
On-Chip Voltage Reference
24-Pin SSOP
APPLICATIONS
American Digital Cellular Telephony
American Analog Cellular Telephony
CMOS, ADC /4 DQPSK
Baseband Transmit Port
AD7011
GENERAL DESCRIPTION
The AD7011 is a complete low power, CMOS, π/4 DQPSK
modulator with single +5 V power supply. The part is designed
to perform the baseband conversion of I and Q transmit wave-
forms in accordance with the American Digital Cellular Tele-
phone system (TIA IS-54).
The on-chip π/4 Differential Quadrature Phase Shift Keying
(DQPSK) digital modulator, which includes the root raised
cosine filters, generates I and Q data in response to the transmit
data stream. The AD7011 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.
Besides providing all the necessary logic to perform π/4 DQPSK
modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7011 generates differential analog outputs for
both the I and Q signals.
As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has transmit and receive power-down
options. The AD7011 is housed in a space efficient 24-pin
SSOP (Shrink Small Outline Package).
MCLK
BIN (Q DATA)
Tx DATA (I DATA)
Tx CLK (FRAME)
READY
POWER
FUNCTIONAL BLOCK DIAGRAM
DGND
VDD
VAA
AGND
I
ANALOG MODE
SERIAL
INTERFACE Q
π /4 DQPSK
DIGITAL
MODULATOR
I
Q
MODULATOR
BYPASS
10-BIT
I-DAC
10-BIT
Q-DAC
RECONSTRUCTION
FILTERS
ITx
ITx
CALIBRATION CIRCUITRY
RECONSTRUCTION
FILTERS
QTx
QTx
AD7011
2.46V
REFERENCE
BOUT
BYPASS MODE1 MODE2
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703


AD7011 데이터시트, 핀배열, 회로
AD7011–SPECIFICATIONS1
(VAA = VDD = +5 V ؎ 10%; Test = AGND = DGND = 0 V; Digital Mode,
fMCLK = 3.1104 MHz; Analog Mode, fMCLK = 2.56 MHz, POWER = VDD. All specifications are TMIN to TMAX unless otherwise noted.)
Parameter
AD7011ARS
Units
Test Conditions/Comments
DIGITAL MODE TRANSMIT SPECIFICATIONS
Number of Channels
Output Signal Range
Differential Output Range
Signal Vector Magnitude2
Error Vector Magnitude2
Offset Vector Magnitude2
IS-54 Spurious Power2, 3
@ 30 kHz
@ 60 kHz
@ 90 kHz, 120 kHz
2
VREF + VREF/4
+VREF/2
0.875 ± 7.5%
1
2.5
0.5
2.5
–35
–30
–70
–65
–75
–70
Volts
Volts
Volts max
% rms typ
% rms max
% typ
% max
dB typ
dB max
dB typ
dB max
dB typ
dB max
(ITx – ITx) and (QTx – QTx)
For Each Analog Output
I Channel = (ITx – ITx) and
Q Channel = (QTx – QTx)
Measured Differentially
ANALOG MODE SPECIFICATIONS
No. of Channels
Resolution
Output Signal Range
Differential Output Range
DAC Update Rate
SNR
Differential Offset Error
Group Delay Matching Between I & Q Outputs
Coding
Maximum and Minimum DAC Codes4
2
10
VREF ± VREF/3
± 2VREF/3
Bits
Volts
Volts
160
60
55
± 15
30
Twos Complement
+450/–450
kHz
dB typ
dB min
mV max
ns typ
max/min
(ITx – ITx) and (QTx – QTx)
For Each Analog Output
I Channel = (ITx – ITx) and
Q Channel = (QTx – QTx)
MCLK/16; fMCLK = 2.56 MHz
Generating a 10 kHz Sine Wave
Post Calibration
REFERENCE & CHANNEL SPECIFICATIONS
Reference, VREF
Reference Accuracy
I and Q Gain Matching
Power-Down Option
2.46
±5
± 0.2
Yes
Volts
%
dB max
Measured @ 10 kHz
Power = 0 V
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
VDD – 0.9
0.9
10
10
V min
V max
FA max
pF max
LOGIC OUTPUTS
VOH Output High Voltage
VOL Output Low Voltage
VDD – 0.4
0.4
V min
V max
|IOUT| 40 µA
|IOUT| 1.6 mA
POWER SUPPLIES
VDD
IDD
Transmit Section Active
Transmit Section Powered Down5
4.5/5.5
8
6
35
5
V min/V max
mA max
mA typ
µA max
µA max
POWER = VDD
MCLK Active
MCLK Inactive
NOTES
1Operating temperature ranges as follows: A Version: –40°C to +85°C.
2See terminology.
3Measured in continuous transmission and Burst Mode with the I and Q channels ramping up and down at the beginning and end of a burst.
4Headroom must be allowed for the transmit DACs such that offsets in I & Q transmit channels can be calibrated out. Therefore, the full range of the I and Q DACs
are not available to the user. The user should ensure that binary codes greater than or less than the maximum or minimum are not loaded into the I or Q DACs.
5Measured while the digital inputs to the transmit interface are static and equal to 0 V or V DD.
Specifications subject to change without notice.
–2– REV. B




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