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PDF AD7008 Data sheet ( Hoja de datos )
| Número de pieza | AD7008 | |
| Descripción | CMOS DDS Modulator | |
| Fabricantes | Analog Devices | |
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a
CMOS
DDS Modulator
AD7008
FEATURES
Single +5 V Supply
32-Bit Phase Accumulator
On-Chip COSINE and SINE Look-Up Tables
On-Chip 10-Bit DAC
Frequency, Phase and Amplitude Modulation
Parallel and Serial Loading
Software and Hardware Power Down Options
20 MHz and 50 MHz Speed Grades
44-Pin PLCC
APPLICATIONS
Frequency Synthesizers
Frequency, Phase or Amplitude Modulators
DDS Tuning
Digital Modulation
PRODUCT DESCRIPTION
The AD7008 direct digital synthesis chip is a numerically con-
trolled oscillator employing a 32-bit phase accumulator, sine and
cosine look-up tables and a 10-bit D/A converter integrated on a
single CMOS chip. Modulation capabilities are provided for
phase modulation, frequency modulation, and both in-phase and
quadrature amplitude modulation suitable for QAM and SSB
generation.
Clock rates up to 20 MHz and 50 MHz are supported. Fre-
quency accuracy can be controlled to one part in 4 billion.
Modulation may be effected by loading registers either through
the parallel microprocessor interface or the serial interface. A
frequency-select pin permits selection between two frequencies
on a per cycle basis.
The serial and parallel interfaces may be operated independently
and asynchronously from the DDS clock; the transfer control
signals are internally synchronized to prevent metastability prob-
lems. The synchronizer can be bypassed to reduce the transfer
latency in the event that the microprocessor clock is synchro-
nous with the DDS clock.
A power-down pin allows external control of a power-down
mode (also accessible through the microprocessor interface)
The AD7008 is available in 44-pin PLCC.
PRODUCT HIGHLIGHT
1. Low Power
2. DSP/µP Interface
3. Completely Integrated
CLOCK
FSELECT
SCLK
SDATA
FUNCTIONAL BLOCK DIAGRAM
VAA GND
FS ADJUST VREF
FREQ0 32
REG
32
MUX
32
12
Σ
FREQ1
REG
32
PHASE
ACCUMULATOR
12
Σ
12
32-BIT SERIAL REGISTER
PHASE REG
IQMOD [19:10]
10
10
SIN
SIN/COS
ROM
10
COS
10
10
Σ
10
10
IQMOD [9:0]
FULLSCALE
ADJUST
10-BIT DAC
32-BIT PARALLEL REGISTER
COMMAND REG
AD7008
COMP
IOUT
IOUT
MPU INTERFACE
TRANSFER LOGIC
D0
D15 WR CS
TC0
TC3 LOAD
TEST
RESET SLEEP
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD7008
PIN DESCRIPTION
Mnemonic Function
POWER SUPPLY
VAA Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between VAA and
AGND. This is +5 V ± 5%.
AGND
Analog Ground.
VDD
DGND
Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between VDD
and DGND. This is +5 V ± 5%. Both VAA and VDD should be externally tied together.
Digital Ground; both AGND and DGND should be externally tied together.
ANALOG SIGNAL AND REFERENCE
IOUT, IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND.
FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the mag-
nitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
6233 ×VREF
IOUTFULL-SCALE (mA) =
RSET
VREF = 1.27 V nominal RSET = 390 Ω typical
VREF
Voltage Reference Input. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA.
There is an internal 1.27 volt reference which can be overdriven by an external reference if required. See
specifications for maximum range.
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF decoupling ceramic
capacitor should be connected between COMP and VAA.
DIGITAL INTERFACE AND CONTROL
CLOCK
Digital Clock Input for DAC and NCO. DDS output frequencies are expressed as a binary fraction of the fre-
quency of this clock. The output frequency accuracy and phase noise is determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. Frequency selection can be done on a cycle-per-cycle basis. See Tables I, II and III.
LOAD
TC3–TC0
Register load, active high digital Input. This pin, in conjunction with TC3–TC0, control loading of internal regis-
ters from either the parallel or serial assembly registers. The load pin must be high at least 1t1. See Table II.
Transfer Control address bus, digital inputs. This address determines the source and destination registers that are
used during a transfer. The source register can either be the parallel assembly register or the serial assembly regis-
ter. The destination register can be any of the following: COMMAND REG, FREQ0 REG, FREQ1 REG,
PHASE REG or IQMOD REG. TC3–TC0 should be valid prior to LOAD rising and should not change until
LOAD falls. The Command Register can only be loaded from the parallel assembly register. See Table II.
CS Chip Select, active low digital input. This input in conjunction with WR is used when writing to the parallel
assembly register.
WR Write, active low digital input. This input in conjunction with CS is used when writing to the parallel assembly
register.
D7–D0
Data Bus, digital inputs. These represent the low byte of the 16-bit data input port used to write to the 32-bit
parallel assembly register. The databus can configured for either a 8-bit or 16-bit MPU/DSP ports.
D15–D8
Data Bus, digital inputs. These represent the high byte of the 16-bit data input port used to write to the 32-bit
parallel assembly register. The databus can be configured for either a 8-bit or 16-bit MPU/DSP ports. When the
databus is configured for 8-bit operation, D8–D15 should be tied to DGND.
SCLK
Serial Clock, digital input. SCLK is used, in conjunction with SDATA, to clock data into the 32-bit serial assem-
bly register.
SDATA
Serial Data, digital input. Serial data is clocked on the rising edge of SCLK, Most Significant Bit (MSB) first.
SLEEP
Low power sleep control, active high digital input. SLEEP puts the AD7008 into a low power sleep mode. Inter-
nal clocks are disabled, while also turning off the DAC current sources. A SLEEP bit is also provided in the
COMMAND REG to put the AD7008 into a low power sleep mode.
RESET
Register Reset, active high digital input. RESET clears the COMMAND REG and all the modulation registers to
zero.
TEST
Test Mode. This is used for factory test only and should be left as a No Connect.
REV. B
–5–
5 Page 
AD7008
cillator application is with the AD607 Monoceiver(tm). This
unique two chip combination provides a complete receiver sub-
system with digital frequency control, RSSI and demodulated
outputs for AM, FM and complex I/Q (SSB or QAM). (See
Figure 13.)
Direct Digital Modulator
In addition to the basic DDS function provided by the AD7008,
the device also offers several modulation capabilities useful in a
wide variety of application. The simplest modulation scheme is
frequency shift keying or FSK. In this application, each of the
two frequency registers is loaded with a different value, one rep-
resenting the space frequency and the other the mark frequency.
The digital data stream is fed to the FSELECT pin causing
the AD7008 to modulate the carrier frequency between the two
values.
1
00
1
0
F SELECT
CLOCK
FREQ 0 32
REG
FREQ 1 32
REG
32
32
MUX
PHASE
ACCUMULATOR
AD7008
Figure 14. FSK Modulator
The AD7008 has three registers that can be used for modula-
tion. Besides the example of frequency modulation shown
above, the frequency registers can be updated dynamically as
can the phase register and the IQMOD register. These can be
modulated at rates up to 16.5 MHz. The example shown below
along with code fragment shows how to implement the AD7008
in an amplitude modulation scheme. Other modulation
schemes can be implemented in a similar fashion.
DSP:
SCALE
ANALOG
ADC INPUT TO
FULL
SCALE
I MOD
10
SIN 10
SIN/COS
ROM
10
COS
10
IOUT
10
10-BIT DAC
10 IOUT
10 10
0 Q MOD
AD7008
Figure 15. Amplitude Modulation
{__________IRQ3 Interrupt Vector__________}
{in_audio is a port used to sample the audio
signal. This signal is assumed to be twos
complement. This interrupt should be serviced
at an audio sample rate. This routine assumes
that the AD7008 has been set up with the Ampli-
tude Modulation Enabled.}
irq3_asserted:
{Get audio sample}
r6=dm(in_audio);
{This section converts the twos complement au-
dio into offset binary scaled for modulating
the AD7008. If twos complement is used, the
modulation scheme will instead be double side-
band, suppressed carrier.}
r5 = 0x80000000;
r6 = r6 xor r5;
r6 = lshift r6 by -1;
r6 = r6 xor r5;
r4 = lshift r6 by -6;
{Load parallel assembly register with modula-
tion data. Q portion set to midscale, I
portion with scaled data}
r5 = 0x00000004;
dm(dds_para) = r5;
dm(dds_para) = r4;
{Transfer parallel assembly register to IQMOD
register}
r4 = 0xb0000000;
dm(dds_cont) = r4;
rti;
Many applications require precise control of the output ampli-
tude, such as in local oscillators, signal generators and modula-
tors. There are several methods to control signal amplitude.
The most direct is to program the amplitude using the IQMOD
register on the AD7008. Other methods include selecting the
load resistor value or changing the value of RSET. Another op-
tion is to place a voltage out DAC on the ground side of RSET as
in Figure 16. This allows easy control of the output amplitude
without affecting other functions of the AD7008. Any combina-
tion of these techniques may be used as long as the full-scale
voltage developed across the load does not exceed 1 volt.
DMDXX–DATA BITS
DMAXX–ADDRESS BITS
+5V
DMS1
DMWR
6
4
5
DMA02
DMA01
DMA00
3
2
1
U1
74HC138
G1
G2A
G2B
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
7
9
10
11
12
13
14
15
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
DMD32
DMD33
DMD34
DMD35
DMD36
DMD37
DMD38
DMD39
DMS3
DMD36
DMD37
DMD38
DMD39
+5V
U2
14 50MHz
VCC
RESET
8
OUT
VEE
7 K1115
U3
AD7008
C1
19 D0
20 D1
21 D2
VREF
6
0.1µF
+5V
C2
5 +5V
22 D3
23 D4
24 D5
COMP
0.1µF
2 R4
25 D6
26 D7
IOUT 49.9
1
8 D8
R3
9 D9
IOUT
49.9
10 D10
11 D11
12 D12
13 D13
14 D14
FSADJUST 4
R5
390
15 D15
16 WR
27
32
33
34
35
36
41
42
31
30
38
37
CS
TC0
TC1
TC2
TC3
LOAD
SCLK
SDATA
FSELECT
CLK
RESET
SLEEP
VAA 3 +5V
VDD 17 +5V
VDD
VDD
28
39
+5V
+5V
AGND
DGND
DGND
DGND
DGND
44
7
18
29
43
TEST 40
VOLTAGE OUT DAC,
i.e., AD7245A
0 TO +1 VOLTS
Ifs = 6233 x (VREF –VDAC)
RSET
Figure 16. External Gain Adjustment
REV. B
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7008.PDF ] | |
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