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PDF ADV7122 Data sheet ( Hoja de datos )
| Número de pieza | ADV7122 | |
| Descripción | CMOS 80 MHz/ Triple 10-Bit Video DACs | |
| Fabricantes | Analog Devices | |
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CMOS
80 MHz, Triple 10-Bit Video DACs
ADV7121/ADV7122
FEATURES
80 MHz Pipelined Operation
Triple 10-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
40-Pin DIP Package (ADV7121)
44-Pin PLCC Package (ADV7122)
48-Lead TQFP (ADV7122)
APPLICATIONS
High Definition Television (HDTV)
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Direct Digital Synthesis (DDS)
I/Q Modulation
SPEED GRADES
80 MHz
50 MHz
30 MHz
GENERAL DESCRIPTION
The ADV7121/ADV7122 (ADV®) is a video speed, digital-to-
analog converter on a single monolithic chip. The part is specifi-
cally designed for high resolution color graphics and video
systems including high definition television (HDTV). It is also
ideal for any application requiring a low cost, high speed DAC
function especially in communications. It consists of three, high
speed, 10-bit, video D/A converters (RGB), a standard TTL input
interface and high impedance, analog output, current sources.
The ADV7121/ADV7122 has three separate, 10-bit, pixel input
ports, one each for red, green and blue video data. A single +5 V
power supply, an external 1.23 V reference and pixel clock input is
all that is required to make the part operational. The ADV7122
has additional video control signals, composite SYNC and BLANK.
The ADV7121/ADV7122 is capable of generating RGB video
output signals which are compatible with RS-343A, RS-170 and
most proposed production system HDTV video standards, in-
cluding SMPTE 240M.
The ADV7121/ADV7122 is fabricated in a +5 V CMOS pro-
cess. Its monolithic CMOS construction ensures greater func-
tionality with low power dissipation. The ADV7121 is packaged
in a 0.6", 40-pin plastic DIP package. The ADV7122 is pack-
ADV is a registered trademark of Analog Devices, Inc.
*Speed grades up to 140 MHz are also available on special request.
Please contact Analog Devices or its representatives for details.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADV7121 FUNCTIONAL BLOCK DIAGRAM
FS
VAA ADJUST VREF
CLOCK
ADV7121
REFERENCE
AMPLIFIER
COMP
R0
R9
PIXEL
INPUT
PORT
G0
G9
B0
B9
RED
10
10 REGISTER
GREEN 10
10 REGISTER
BLUE
10
10 REGISTER
DAC
DAC
DAC
IOR
IOG
IOB
GND
ADV7122 FUNCTIONAL BLOCK DIAGRAM
FS
VAA ADJUST VREF
CLOCK
ADV7122
REFERENCE
AMPLIFIER
COMP
R0
R9
PIXEL
INPUT
PORT
G0
G9
B0
B9
RED 10
10 REGISTER
GREEN 10
10 REGISTER
BLUE 10
10 REGISTER
DAC
DAC
DAC
IOR
IOG
IOB
BLANK
SYNC
CONTROL
REGISTER
SYNC
CONTROL
GND
aged in a 44-pin plastic leaded (J-lead) chip carrier, PLCC,
and 48-lead thin quad flatpack (TQFP).
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 80 MHz.
2. Guaranteed monotonic to 10 bits. Ten bits of resolution al-
lows for implementation of linearization functions such as
gamma correction and contrast enhancement.
3. Compatible with a wide variety of high resolution color
graphics systems including RS-343A/RS-170 and the pro-
posed SMPTE 240M standard for HDTV.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
ABSOLUTE MAXIMUM RATINGS1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on Any Digital Pin . . . . . GND –0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Soldering Temperature (5 secs) . . . . . . . . . . . . . . . . . . . 220°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220°C
IOR, IOB, IOG to GND2 . . . . . . . . . . . . . . . . . . . 0 V to VAA
ADV7121/ADV7122
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Analog output short circuit to any power supply or common can be of an indefinite
duration.
DIP (N-40A) Package
PIN CONFIGURATIONS
PLCC (P-44A) Package
R6 1
R7 2
R8 3
R9 4
G0 5
G1 6
G2 7
G3 8
G4 9
G5 10
G6 11
G7 12
G8 13
G9 14
VAA 15
B0 16
B1 17
B2 18
B3 19
B4 20
ADV7121 DIP
TOP VIEW
(Not to Scale)
40 R5
39 R4
38 R3
37 R2
36 R1
35 R0
34 FS ADJUST
33 VREF
32 COMP
31 IOR
30 IOG
29 VAA
28 IOB
27 GND
26 CLOCK
25 B9
24 B8
23 B7
22 B6
21 B5
6 5 4 3 2 1 44 43 42 41 40
G1 7
G2 8
G3 9
G4 10
G5 11
G6 12
G7 13
G8 14
G9 15
BLANK 16
SYNC 17
ADV7122 PLCC
TOP VIEW
(Not to Scale)
39 FS ADJUST
38 VREF
37 COMP
36 IOR
35 IOG
34 VAA
33 VAA
32 IOB
31 GND
30 GND
29 CLOCK
18 19 20 21 22 23 24 25 26 27 28
ORDERING GUIDE
Model
Speed
Temperature Package
Range*
Description
Package
Option
ADV7121KN80 80 MHz 0°C to +70°C
ADV7121KN50 50 MHz 0°C to +70°C
ADV7121KN30 30 MHz 0°C to +70°C
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
N-40A
N-40A
N-40A
ADV7122KP80 80 MHz 0°C to +70°C
ADV7122KP50 50 MHz 0°C to +70°C
ADV7122KP30 30 MHz 0°C to +70°C
44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A
44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A
44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A
ADV7122KST50 50 MHz 0°C to +70°C 48-Lead Thin Quad Flatpack (TQFP)
ADV7122KST30 30 MHz 0°C to +70°C 48-Lead Thin Quad Flatpack (TQFP)
ST-48
ST-48
*Industrial Temperature range (–40°C to +85°C) parts are also available to special ranges. Please contact your local Analog Devices
representative.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7121/ADV7122 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, p roper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
5 Page 
ADV7121/ADV7122
VIDEO
DATA
INPUTS
VIDEO
CONTROL
INPUTS
COMP
R0
R9 VAA
G0
G9
B0
B9 VREF
ADV7121/ADV7122
GND
C6
0.1µF
ANALOG POWER PLANE
C3
0.1µF
C4
0.1µF
RSET
560Ω
R1
75Ω
R2
75Ω
C5
0.1µF
L1 (FERRITE BEAD)
+5V (VCC)
Z1 (AD589)
C2
10µF
C1
33µF
ANALOG GROUND PLANE
L2 (FERRITE BEAD)
R3
75Ω
GROUND
FS ADJUST
CLOCK
SYNC*
IOR
IOG
RGB
VIDEO
OUTPUT
BLANK*
IOB
*SYNC and BLANK FUNCTIONS ARE NOT PROVIDED ON THE ADV7121.
COMPONENT
C1
C2
C3, C4, C5, C6
L1, L2
R1, R2, R3
RSET
Z1
DESCRIPTION
33µF TANTALUM CAPACITOR
10µF TANTALUM
0.1µF CERAMIC CAPACITOR
FERRITE BEAD
75Ω 1% METAL FILM RESISTOR
560Ω 1% METAL FILM RESISTOR
1.235V VOLTAGE REFERENCE
VENDOR PART NUMBER
FAIR-RITE 274300111 OR MURATA BL01/02/03
DALE CMF-55C
DALE CMF-55C
ANALOG DEVICES AD589JH
Figure 8. ADV7121/ADV7122 Typical Connection Diagram and Component List
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 8).
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA should be individually
decoupled to ground. This should be done by placing the ca-
pacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV7121/ADV7122 con-
tains circuitry to reject power supply noise, this rejection de-
creases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduce
ing power supply noise. A dc power supply filter (Murata
BNX002) will provide EMI suppression between the switching
power supply and the main PCB. Alternatively, consideration
could be given to using a three terminal voltage regulator.
Digital Signal Interconnect
The digital signal lines to the ADV7121/ADV7122 should be
isolated as much as possible from the analog outputs and other
analog circuitry. Digital signal lines should not overlay the ana-
log power plane.
Due to the high clock rates used, long clock lines to the
ADV7121/ADV7122 should be avoided so as to minimize noise
pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (VCC),
and not the analog power plane.
Analog Signal Interconnect
The ADV7121/ADV7122 should be located as close as possible
to the output connectors thus minimizing noise pickup and re-
flections due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
should be as close as possible to the ADV7121/ADV7122 so as
to minimize reflections.
Additional information on PCB design is available in an appli-
cation note entitled “Design and Layout of a Video Graphics
System for Reduced EMI.” This application note is available
from Analog Devices, publication no. E1309–15–10/89.
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADV7122.PDF ] | |
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