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74ALVC16240 반도체 회로 부품 판매점

Low-Voltage 1.8/2.5/3.3V 16-Bit Buffer



ON Semiconductor 로고
ON Semiconductor
74ALVC16240 데이터시트, 핀배열, 회로
74ALVC16240
Low−Voltage 1.8/2.5/3.3 V
16−Bit Buffer
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Inverting)
The 74ALVC16240 is an advanced performance, inverting 16−bit
buffer. It is designed for very high−speed, very low−power operation
in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVC16240 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16−bit operation. The 3−state outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state.
Designed for Low Voltage Operation: VCC = 1.65−3.6 V
3.6V Tolerant Inputs and Outputs
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±250 mA @ 125°C
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
Second Source to Industry Standard 74ALVC16240
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to VCC through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
74ALVC16240DT
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
74ALVC16240DTR TSSOP 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 1
1
Publication Order Number:
74ALVC16240/D


74ALVC16240 데이터시트, 핀배열, 회로
OE1 1
O0 2
O1 3
GND 4
O2 5
O3 6
VCC 7
O4 8
O5 9
GND 10
O6 11
O7 12
O8 13
O9 14
GND 15
O10 16
O11 17
VCC 18
O12 19
O13 20
GND 21
O14 22
O15 23
OE4 24
48 OE2
47 D0
46 D1
45 GND
44 D2
43 D3
42 VCC
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
31 VCC
30 D12
29 D13
28 GND
27 D14
26 D15
25 OE3
Figure 1. 48−Lead Pinout
(Top View)
PIN NAMES
Pins
Function
OEn
D0−D15
O0−O15
Output Enable Inputs
Inputs
Outputs
74ALVC16240
1
OE1
48
OE2
25
OE3
24
OE4
D0:3 O0:3 D8:11 O8:11
D4:7 O4:7 D12:15 O12:15
One of Four
Figure 2. Logic Diagram
1
OE1
OE2 48
25
OE3
24
OE4
EN1
EN2
EN3
EN4
D0 47
D1 46
D2 44
D3 43
D4 41
D5 40
D6 38
D7 37
D8 36
D9 35
D10 33
D11 32
D12 30
D13 29
D14 27
D15 26
1 1
1 2
1 3
1 4
2 O0
3 O1
5 O2
6 O3
8 O4
9 O5
11 O6
12 O7
13 O8
14 O9
16 O10
17 O11
19 O12
20 O13
22 O14
23 O15
Figure 3. IEC Logic Diagram
OE1
D0:3
O0:3
OE2
D4:7
O4:7
OE3
D8:11
O8:11
OE4 D12:15 O12:15
L L H LL H LL H LL H
L H L LH L LH L LH L
H X Z HX Z HX Z HX Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for
ICC reasons, DO NOT FLOAT Inputs
http://onsemi.com
2




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74ALVC16240 buffer

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