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PDF V826632K24SA Data sheet ( Hoja de datos )
| Número de pieza | V826632K24SA | |
| Descripción | 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE | |
| Fabricantes | ProMOS TECHNOLOGIES | |
| Logotipo |  |
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V826632K24SA
32M x 64 HIGH PERFORMANCE
UNBUFFERED DDR SDRAM MODULE
Features
■ 184 Pin Unbuffered 33,554,432 x 64 bit
Organization DDR SDRAM Modules
■ Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
■ Single +2.5V (± 0.2V) Power Supply
■ Single +2.6V (± 0.1V) Power Supply for DDR400
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are SSTL-2 Compatible
■ 8192 Refresh Cycles every 64 ms
■ Serial Presence Detect (SPD)
■ DDR SDRAM Performance
Component Used D3 C0 B1 B0
tCK Clock Frequency
200
166
143 133
(max.)
(PC400) (PC333) (PC266A) (PC266B)
Module Speed
D0
tAC
Clock Cycle Time
6
CAS CLaloteckncFyre=q2u.e5ncy (max.)
6
7 7.5
200
(PC400A)
tAC ClockCCloycckleCTyicmleeTime C5AS Laten-cy = 2 -
tCCKAS
Latency = 3
Clock Cycle
Time
CAS
Latency
=
2.5
-7.5
5
Clock Cycle Time CAS Latency = 3
5
tRCD tRCD parameter
tRP tRP parameter
3
3
Description
The V826632K24SA memory module is
organized 33,554,432 x 64 bits in a 184 pin memory
module. The 32M x 64 memory module uses 8
ProMOS 32M x 8 DDR SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
D3
200
(PC400B)
7.5
6
5
3
3
C0
166
(PC333)
7.5
6
-
3
3
B1
143
(PC266A)
7.5
7
-
2
2
B0
133
(PC266B)
10
7.5
-
3
3
Units
MHz
ns
ns
ns
CLK
CLK
V826632K24SA Rev. 1.3 April 2006
1
1 page  
ProMOS TECHNOLOGIES
Serial Presence Detect Information
Bin Sort:
D0 (PC3200 @ CL 2.5-3-3)
D3 (PC3200 @ CL 3-3-3)
C0 (PC2700 @ CL 2.5-3-3)
V826632K24SA
B1 (PC2100A @ CL 2-2-2)
B0 (PC2100B @ CL 2.5-3-3)
Byte
#
Function described
Function Supported
D0 D3 C0 B1 B0
Hex value
D0 D3 C0 B1 B0
0 Defines # of Bytes written into serial memory at
module manufacturer
128bytes
80h
1 Total # of Bytes of SPD memory device
256bytes
08h
2 Fundamental memory type
SDRAM DDR
07h
3 # of row address on this assembly 13 0Dh
4 # of column address on this assembly
10
0Ah
5 # of module Rows on this assembly
1 Bank
01h
6 Data width of this assembly
64 bits
40h
7 .........Data width of this assembly
- 00h
8 VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9 DDR SDRAM cycle time at highest CAS Latency 5ns 5ns 6ns 7ns 7.5ns 50h 50h 60h 70h 75h
10 DDR SDRAM Access time from clock at highest ±0.65ns ±0.65ns ±0.70ns ±0.75ns ±0.75ns 65h 65h 70h 75h 75h
CL
11 DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
00h
12 Refresh rate & type
7.8us & Self refresh
82h
13 Primary DDR SDRAM width
x8 08h
14 Error checking DDR SDRAM data width
N/A
00h
15 Minimum clock delay for back-to-back random
column address
tCCD=1CLK
01h
16 DDR SDRAM device attributes : Burst lengths
supported
2,4,8
0Eh
17 DDR SDRAM device attributes : # of banks on
each DDR SDRAM
4 banks
04h
18 DDR SDRAM device attributes : CAS Latency
supported
2,2.5,3
1Ch 1Ch 0Ch 0Ch 0Ch
19 DDR SDRAM device attributes : CS Latency
0CLK
01h
20 DDR SDRAM device attributes : WE Latency
1CLK
02h
21 DDR SDRAM module attributes
Differential clock /
non Registered
20h
22 DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23 DDR SDRAM cycle time at second highest CL 5.0ns 6.0ns 7.5ns 7.5ns 10ns 50h 60h 75h 75h A0h
24 DDR SDRAM Access time from clock at second ±0.65ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns 65h 70h 70h 75h 75h
highest CL
V826632K24SA Rev.1.3 April 2006
5
5 Page 
ProMOS TECHNOLOGIES
V826632K24SA
AC Characteristics (cont.)
Parameter
Sym-
bol
(PC400A)
D0
Min Max
(PC400B)
D3
Min Max
(PC333)
C0
Min Max
(PC266A)
B1
Min Max
(PC266B)
B0 Units
Min Max
Note
CLK to First Rising edge of DQS-In tDQSS 0.72 1.25 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
Data-In Setup Time to DQS-In (DQ tDS 0.40 - 0.40 - 0.45 - 0.5 - 0.5 - tCK
& DM)
7
Data-in Hold Time to DQS-In (DQ & tDH 0.40 - 0.40 - 0.45 - 0.5 - 0.5 - tCK 7
DM)
DQ & DM Input Pulse Width
tDIPW 1.75 - 1.75 - 1.75 - 1.75 - 1.75 - tCK
Read DQS Preamble Time
tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read DQS Postamble Time
tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Write DQS Preamble Setup Time tWPRES 0 - 0 - 0 - 0 - 0 - tCK
Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - tCK
Write DQS Postamble Time
tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
2
-
2
- tCK
Power Down Exit Time to any com- tXPDN 1 - 1 - 1 - 1 - 1 - tCK
mand
Exit Self Refresh to Non-Read
Command
tXSNR 200 - 200 - 200 - 200 - 200 - tCK 8
Average Periodic Refresh Interval tREFI - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
V826632K24SA Rev.1.3 April 2006
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet V826632K24SA.PDF ] | |
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