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ICS671-03 반도체 회로 부품 판매점

Low Skew Buffer



Integrated Circuit Systems 로고
Integrated Circuit Systems
ICS671-03 데이터시트, 핀배열, 회로
PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
Description
The ICS671-03 is a low phase noise, high speed PLL
based, 8 output, low skew zero delay buffer. Based on
ICS’s proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides eight low skew
outputs at speeds up to 133 MHz at 3.3 V. The
outputs can be generated from the PLL (for zero
delay), or directly from the input (for testing), and can
be set to tri-state mode or to stop at a low level. For
normal operation as a zero delay buffer, any output
wwwc.DloactakSihseteiet4dUt.ocothme FBIN pin.
ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Clock outputs from 10 to 133 MHz
• Zero input-output delay
• Eight low-skew (<200 ps) outputs
• Device-to-device skew <700 ps
• Low jitter (<200 ps)
• Full CMOS outputs with 25 mA output drive
capability at TTL levels
• 5 V tolerant FBIN and CLKIN pins
• Tri-state mode for board-level testing
• Advanced, low power, sub-micron CMOS process
• 3.3 V operating voltage
• Industrial temperature range of -40 to 85 °C
Block Diagram
S2, S1
2
CLKIN
FBIN
Control
Logic
Clock
Synthesis
PLL
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Feedback is shown from CLKB4 for illustration, but may
come from any output.
MDS 671-03 A 1 Revision 072501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com


ICS671-03 데이터시트, 핀배열, 회로
Pin Assignment
PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
www.DataSheeCt4LU.KcBom2
S2
1
2
3
4
5
6
7
8
16 FBIN
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
16 pin narrow (150 mil) SOIC
Output Clock Mode Select Table
S2 S1
CLKA1:A4
CLKB1:B4
00
Tri-state (Note 1)
Tri-state (Note 1)
01
Stopped Low
Stopped Low
10
Running
Running
11
Running
Running
Notes: 1. Outputs are in high impedance state with weak pulldowns.
2. Buffer mode only; not zero delay between input and output.
Pin Descriptions
A & B Source
PLL
none
CLKIN (Note 2)
PLL
PLL Status
ON
OFF
OFF
ON
Number
1
2, 3, 14, 15
4, 13
5, 12
6, 7, 10, 11
8
9
16
Name
CLKIN
CLKA1:A4
VDD
GND
CLKB1:B4
S2
S1
FBIN
Type
I
O
P
P
O
I
I
I
Description
Clock Input. (5 V tolerant)
Clock Outputs A1:A4. See above table. Outputs have weak pulldown resistors.
Power supply. Connect both pins to 3.3 V.
Connect to ground.
Clock Outputs B1:B4. See above table. Outputs have weak pulldown resistors.
Select input 2. See table above. Internal pull-up.
Select input 1. See table above. Internal pull-up.
Feedback Input. Connect to any output under normal operation. (5 V tolerant)
Key: I = Input; O = output; P = power supply connection. Outputs have a weak internal pull-down when in tri-state
mode.
External Components
The ICS671-03 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on pins 13 and 12, as
close to the device as possible. A series termination resistor of 33 may be used close to each clock output pin to
reduce reflections.
MDS 671-03 A 2 Revision 072501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com




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