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RD74LVC1G240 반도체 회로 부품 판매점

Bus Buffer Inverted



Renesas Technology 로고
Renesas Technology
RD74LVC1G240 데이터시트, 핀배열, 회로
RD74LVC1G240
www.DataSheet4U.com
Bus Buffer Inverted with 3–state Output
Description
REJ03D0733–0100
Rev.1.00
Apr 13, 2006
The RD74LVC1G240 has bus buffer inverted with 3–state output in a 5-pin package. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption
extends the battery life.
Features
The basic gate function is lined up as renesas uni logic series.
Supply voltage range: 1.65 to 5.5 V
Operating temperature range: –40 to +85°C
All inputs: VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs: VO (Max.) = 5.5 V (@VCC = 0 V)
Output current:
±4 mA (@VCC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±24 mA (@VCC = 3.0 V)
±32 mA (@VCC = 4.5 V)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
RD74LVC1G240WPE
WCSP–5 pin SXBG0005LB–A
(TBS–5CV)
Package
Abbreviation
WP
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Article Indication
Marking
Year code
EHYM
Month code
Rev.1.00 Apr 13, 2006 page 1 of 7


RD74LVC1G240 데이터시트, 핀배열, 회로
RD74LVC1G240
Function Table
OE
L
L
H
H: High level
L: Low level
X: Immaterial
Z: High impedance
Inputs
Pin Arrangement
0.7 mm
Height 0.4 mm
0.4 mm pitch
0.17 mm 5–Ball (WP) GND
34
A
L
H
X
Y
A2
OE 1 5 VCC
www.DataSheet4U.com
Output Y
H
L
Z
Pin#1 INDEX
Logic Diagram
(Bottom view)
OE 1
2
A
(Top view)
4
Y
Rev.1.00 Apr 13, 2006 page 2 of 7




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RD74LVC1G240 buffer

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Bus Buffer Inverted - Renesas Technology