파트넘버.co.kr 74AUP2G07 데이터시트 PDF


74AUP2G07 반도체 회로 부품 판매점

Low-power dual buffer



NXP Semiconductors 로고
NXP Semiconductors
74AUP2G07 데이터시트, 핀배열, 회로
www.DataSheet4U.com
74AUP2G07
Low-power dual buffer with open-drain output
Rev. 02 — 12 June 2007
Product data sheet
1. General description
The 74AUP2G07 provides two non-inverting buffers with open-drain output. The output of
the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114E Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101C exceeds 1000 V
s Low static-power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C


74AUP2G07 데이터시트, 핀배열, 회로
www.DNatXaSPheSete4Um.coicmonductors
74AUP2G07
Low-power dual buffer with open-drain output
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP2G07GW 40 °C to +125 °C SC-88
74AUP2G07GM 40 °C to +125 °C XSON6
74AUP2G07GF 40 °C to +125 °C XSON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP2G07GW
74AUP2G07GM
74AUP2G07GF
5. Functional diagram
Marking code
p7
p7
p7
1 1A
1Y 6
3 2A
2Y 4
mnb092
Fig 1. Logic symbol
1A 1
6 1Y
2A 3
4 2Y
mnb093
Fig 2. IEC logic symbol
Y
A
GND
mna625
Fig 3. Logic diagram (one gate)
74AUP2G07_2
Product data sheet
Rev. 02 — 12 June 2007
© NXP B.V. 2007. All rights reserved.
2 of 16




PDF 파일 내의 페이지 : 총 16 페이지

제조업체: NXP Semiconductors

( nxp )

74AUP2G07 buffer

데이터시트 다운로드
:

[ 74AUP2G07.PDF ]

[ 74AUP2G07 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


74AUP2G00

Low-power dual 2-input NAND gate - NXP Semiconductors



74AUP2G00

DUAL NAND GATE - Diodes



74AUP2G02

DUAL NOR GATE - Diodes



74AUP2G02

Low-power Dual 2-input NOR Gate - NXP Semiconductors



74AUP2G04

Low-power dual inverter - NXP Semiconductors



74AUP2G04

DUAL INVERTERS - Diodes



74AUP2G06

DUAL INVERTERS - Diodes



74AUP2G07

Low-power dual buffer - NXP Semiconductors



74AUP2G07

DUAL BUFFERS - Diodes