|
|
PDF ICS8344 Data sheet ( Hoja de datos )
| Número de pieza | ICS8344 | |
| Descripción | 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS8344 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8344
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8344 is a low voltage, low skew fanout
,&6 buffer and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The ICS8344 is designed to translate any
differential signal levels to LVCMOS levels. The
low impedance LVCMOS outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased to 48 by utilizing the ability of the
www.DataSheeot4uUtp.cuotms to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual
clock inputs also facilitate board level testing. ICS8344 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
FEATURES
• 24 LVCMOS outputs, 7Ω typical output impedance
• Output frequency up to 167MHz
• 275ps output skew, 600ps part to part skew
• Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS without external bias networks
• Translates any single-ended input signal to LVCMOS with
resistor bias on nCLK input
• Translates and inverts any single-ended input signal to
LVCMOS with resistor bias on CLK input
• Multiple differential clock input pairs for redundant clock
applications
• LVCMOS control inputs
• Multiple output enable pins for disabling unused outputs in
reduced fanout applications
• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
• 48 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
• 0°C to 70°C ambient operating temperature
• Industrial temperature versions available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
OE1
OE2
OE3
0
1
Q0 - Q7
O8 - Q15
O16 - Q23
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6
7
ICS8344
31
30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
48-Lead LQFP
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8344
www.icst.com
REV. B FEBRUARY 2, 2001
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8344
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX Maximum Input Frequency
167
VPP Peak-to-Peak Input Voltage
f = 167MHz
0.3
1.3
VCMR Common Mode Input Voltage
f = 167MHz
0.9
2
tpLH Propagation Delay, Low-to-High
0MHz ≤ f ≤ 167MHz
2.6
4.3
www.DataSheet4tpUH.cLom Propagation Delay, High-to-Low
0MHz ≤ f ≤ 167MHz
2.4
4.3
tsk(b) Bank Skew; NOTE 2
Measured on the rising edge of
VDDO/2
150
tsk(o) Output Skew; NOTE 3
Measured on the rising edge of
VDDO/2
275
tsk(pp) Part-to-Part Skew; NOTE 4
Measured on the rising edge of
VDDO/2
600
tR Output Rise Time; NOTE 5
30% to 70%
200
1000
tF Output Fall Time; NOTE 5
30% to 70%
200
1000
tPW Output Pulse Width
0MHz ≤ f ≤ 167MHz
f = 167MHz
tCYCLE/2-
- 0.65
2.35
tCYCLE/2
2.5
tCYCLE/2
+ 0.65
3.65
tEN Output Enable Time; NOTE 5
f = 66.7MHz
5
tDIS Output Disable TIme; NOTE 5
f = 66.7MHz
4
NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise.
All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages
with equal load conditions.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
MHz
V
V
ns
ns
ps
ps
ps
ps
ps
ns
ns
ns
ns
8344
www.icst.com
5
REV. B FEBRUARY 2, 2001
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8344
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 2A, 2B - TIMING WAVEFORMS
www.DataSheet4U.com
CLK
nCLK
Q
VDDO/2
VPP
tPHL
tPLH
FIGURE 2A - PROPAGATION DELAYS
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
OEx 3.3V
OEx
0V
Q VOH
VDDO/2
VDDO/2
Q VOL
tPHZ
VOH - 300mV
tPLZ
VOL + 300mV
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
tPZH
tPZL
8344
www.icst.com
11
REV. B FEBRUARY 2, 2001
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS8344.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS8343 | Low Skew 1-to-16 Fanout Buffer | Integrated Circuit Systems |
| ICS8343-01 | 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER | Integrated Circuit Systems |
| ICS8343I | LOW SKEW 1-TO-16 FANOUT BUFFER | Integrated Circuit Systems |
| ICS8343I-01 | 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |