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Integrated Circuit Systems |
Integrated
Circuit
Systems, Inc.
ICS8343-01
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8343-01 is a low skew, 1-to-16 LVCMOS/
LVTTL Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS8343-01 single ended
clock input accepts LVCMOS or LVTTL input levels.
The ICS8343-01 operates at 3.3V, 2.5V and mixed 3.3V input and
2.5V supply modes over the commercial temperature range.
Guaranteed output and part-to-part skew characteristics make
www.DataSheetth4eU.IcCoSm8343-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
• 16 LVCMOS/LVTTL outputs
• 1 LVCMOS/LVTTL clock input
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 200MHz
• Dual output enable inputs facilitates 1-to-16 or 1-to-8 input
to output modes
• All inputs are 5V tolerant
• Output skew: 250ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
VVDDDD11 VVDDDD
CCLLKK
QQ00
QQ11
QQ22
QQ33
QQ44
QQ55
QQ66
QQ77
VVDDDD22
QQ155
QQ144
QQ133
QQ122
QQ111
QQ1100
QQ99
QQ8
OOEE11
GGNNDD
OOEE22
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
VDD1
VDD1
VDD1
Q3
Q4
GND
GND
GND
1
2
3
4
5
6
7
8
ICS8343-01
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
VDD2
VDD2
VDD2
Q12
Q11
GND
GND
GND
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
(Top View)
8343AY-01
www.icst.com/products/hiperclocks.html
1
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS8343-01
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 3
4, 5
VDD1
Q3, Q4
Power
Output
Q0 thru Q7 output supply pins.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
6, 7, 8,
17, 18, 19
GND
Power
Power supply ground.
9, 10, 11 Q5, Q6, Q7 Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
12
www.DataSheet4U.com
13
14, 15, 16
CLK
V
DD
Q8, Q9, Q10
Input
Power
Output
Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
Core supply pin.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
20, 21
Q11, Q12
Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
22, 23, 24
VDD2
Power
25, 26, 27 Q13, Q14, Q15 Output
Q8 thru Q15 output supply pins.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
28
OE2
Input
Pullup
Output enable. When low forces outputs Q8 thru Q15 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
29
OE1
Input
Pullup
Output enable. When low forces outputs Q0 thru Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
30, 31, 32 Q0, Q1, Q2 Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD, VDD1, VDD2 = 3.465V
VDD1, VDD2 = 2.63V
VDD, VDD1, VDD2 = 3.3V
Minimum
5
Typical
4
11
9
51
51
7
Maximum
12
Units
pF
pF
pF
KΩ
KΩ
Ω
TABLE 3. FUNCTION TABLE
Inputs
Outputs
OE1
OE2
Q0:Q7
Q8:Q15
0 0 HiZ HiZ
1
0
Active
HiZ
0 1 HiZ Active
1
1
Active
Active
NOTE: OE1 and OE2 are 5V tolerant.
8343AY-01
www.icst.com/products/hiperclocks.html
2
REV. B SEPTEMBER 16, 2004
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