NB3N2304NZ 반도체 회로 부품 판매점
3.3V 1:4 Clock Fanout Buffer
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 ON Semiconductor |
NB3N2304NZ
3.3V 1:4 Clock Fanout
Buffer
Description
The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer,
designed for high speed clock distribution such as in PCI−X
applications. The NB3N2304NZ guarantees low output−to−output
skew. Optimal design, layout and processing minimizes skew within a
device and from device−to−device.
The Output Enable (OE) pin forces the outputs LOW when LOW.
Features
• Input/Output Clock Frequency up to 140 MHz
• Low Skew Outputs (100 ps)
• Output Enable
• Operating Range: VDD = 3.0 V to 3.6 V
• Ideal for PCI−X and networking clocks
• Packaged in 8−pin TSSOP, 4.4 mm x 3 mm
• Industrial Temperature Range
• These are Pb−Free Devices*
http://onsemi.com
MARKING
DIAGRAM*
TSSOP−8
DT SUFFIX
CASE 948S
40N
YWW
AG
1
DFN8
MN SUFFIX
CASE 506AA
14
A = Assembly Location
Y = Year
WW = Work Week
M = Date Code
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 6
1
Publication Order Number:
NB3N2304NZ/D
OE
Logic
Control
Q1
Q2
IN
Q3
Q4
Figure 2. Block Diagram
NB3N2304NZ
IN
OE
Q1
GND
1
2
3
4
8 Q4
7 Q3
6 VDD
5 Q2
Figure 3. NB3N2304NZ Package Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin #
Pin
Name
Type
1 IN LVCMOS/LVTTL Input
2 OE LVCMOS/LVTTL Input
3 Q1 LVCMOS/LVTTL Output
4 GND
Power
5 Q2 (LV)CMOS/(LV)TTL Input
6 VDD
Power
7 Q3 (LV)CMOS/(LV)TTL Output
8 Q4 (LV)CMOS/(LV)TTL Input
− EP Thermal Exposed Pad
Description
Clock Input
Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs
are forced to logic LOW when OE is forced LOW.
Clock Output 1
Negative Supply Voltage; Connect to Ground, 0 V
Clock Output 2
Positive Supply Voltage (3.0 V to 3.6 V)
Clock Output 3
Clock Output 4
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit.
Electrically connect to the most negative supply (GND) or leave unconnected, floating
open.
Table 2. OE, OUTPUT ENABLE FUNCTION TABLE
Inputs
IN OE
LL
HL
LH
HH
Outputs
L
L
L
H
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2
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( onsemi )
NB3N2304NZ buffer
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