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PDF 74VHCT16244A Data sheet ( Hoja de datos )
| Número de pieza | 74VHCT16244A | |
| Descripción | 16-BIT BUS BUFFER | |
| Fabricantes | ST Microelectronics | |
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74VHCT16244A
16-BIT BUS BUFFER
WITH 3-STATE OUTPUTS (NON INVERTED)
s HIGH SPEED:
tPD = 5.4 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS:
VIH =2V (MIN.) VIL = 0.8 (MAX.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16244
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTION
The 74VHCT16244A is an advanced high-speed
CMOS 16-BIT BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS tecnology.
Any nG output control governs four BUS
BUFFERS. Output Enable inputs (nG) tied
together give full 16 bit operation.
When nG is LOW, the outputs are enabled. When
nG is HIGH, the output are in high impedance
state.
The device is designed to be used with 3-state
memory address drivers, etc.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74VHCT16244ATTR
February 2003
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74VHCT16244A
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
VOLP
VOLV
Dynamic Low
Voltage Quiet
Output (note 1, 2)
5.0
0.6 0.9
-0.9 -0.6
V
VIHD
Dynamic High
Voltage Input
(note 1, 3)
5.0 CL = 50 pF 3.5
V
VILD
Dynamic Low
Voltage Input
(note 1, 3)
5.0
1.5 V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
TEST CIRCUIT
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
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SWITCH
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VCC
GND
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