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PDF AD5060 Data sheet ( Hoja de datos )
| Número de pieza | AD5060 | |
| Descripción | Full Accurate 14/16 Bit Vout nanoDac Buffered | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5060 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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Fully Accurate 14-/16-Bit VOUT nanoDAC™
SPI Interface 2.7 V to 5.5 V, in an SOT-23
AD5040/AD5060
FEATURES
Single 14-/16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically
2.7 V to 5.5 V power supply
Low glitch on power-up
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5040 and the AD5060, members of the ADI nanoDAC
family, are low power, single 14-/16-bit buffered voltage-out
DACs that operate from a single 2.7 V to 5.5 V supply. The
AD5040/AD5060 parts offer a relative accuracy specification
of ±1 LSB and operation are guaranteed monotonic with a
±1 LSB DNL specification. The parts use a versatile 3-wire serial
interface that operates at clock rates up to 30 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The reference for both the AD5040
and AD5060 is supplied from an external VREF pin. A reference
buffer is also provided on-chip. The AD5060 incorporates a
power-on reset circuit that ensures the DAC output powers up
to midscale or zero scale and remains there until a valid write
takes place to the device. The AD5040 and the AD5060 both
contain a power-down feature that reduces the current con-
sumption of the device to typically 330 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The parts are put into power-down mode over the serial
interface. Total unadjusted error for the parts is <2 mV.
Both parts exhibit very low glitch on power-up.
FUNCTIONAL BLOCK DIAGRAM
VREF
VDD
POWER-ON
RESET
BUF
DAC
REGISTER
REF(+)
DAC
OUTPUT
BUFFER
AD5040/
AD5060
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
AGND
SYNC SCLK DIN
DACGND
Figure 1.
PRODUCT HIGHLIGHTS
1. Available in a small, 8-lead SOT-23 package.
2. 14-/16-bit accurate, 1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 30 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (midscale, zero scale).
Table 1. Related Devices
Part No. Description
AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSB INL, SOT-23
AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A,1 LSB INL, SOT-23
AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, MSOP
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005-2010 Analog Devices, Inc. All rights reserved.
1 page  
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
Limit1
33
5
3
10
3
2
0
12
9
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
SCLK
SYNC
DIN
t4
t8
D23
t2 t1
t3
t6
t5
D22 D2 D1
t9
t7
D0
Figure 2. AD5060 Timing Diagram
AD5040/AD5060
D23 D22
Rev. A | Page 5 of 24
5 Page 
3.00
TA = 25°C
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0 10000
20000
VDD = 5.5V, VREF = 4.096V
VDD = 3.0V, VREF = 2.5V
30000 40000 50000 60000 70000
DAC CODE
Figure 22. Typical Supply Current vs. Digital Input Code1
24TH CLOCK FALLING
CH1 = SCLK
CH2 = VOUT
CH2 50mV/DIV CH1 2V/DIV TIME BASE 400ns/DIV
Figure 23. AD5060 Digital-to-Analog Glitch Impulse
(See Figure 24)
0.117
0.116
0.115
0.114
0.113
0.112
0.111
0.110
0.109
0.108
0.107
0.106
0.105
0.104
0.103
0.102
0.101
VDD = 5V
VREF = 4.096V
R = 5kΩ
C = 220pF
CODE = 57386
SAMPLES
Figure 24. AD5060 Digital-to-Analog Glitch Energy
1 AD5060 only.
VDD = 3V
DAC = FULL SCALE
VREF = 2.7V
TA = 25°C
AD5040/AD5060
Y AXIS = 2μV/DIV
X AXIS = 4s/DIV
Figure 25. 0.1 Hz to 10 Hz Noise Plot
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
REFERENCE VOLTAGE (V)
Figure 26. VDD Headroom vs. Reference Voltage
5.05
5.00
4.95
VDD = 5.0V
TA = 25°C
DAC = FULL-SCALE
4.90
4.85
4.80
4.75
4.70
4.65
4.60
4.55
4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00
VREF (V)
Figure 27. Output Voltage vs. Reference Voltage
Rev. A | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5060.PDF ] | |
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