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PDF 74VHC541 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC541 | |
| Descripción | OCTAL BUS BUFFER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74VHC541
OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (NON INVERTED)
s HIGH SPEED: tPD = 3.5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
)s POWER DOWN PROTECTION ON INPUTS
t(ss SYMMETRICAL OUTPUT IMPEDANCE:
c|IOH| = IOL = 8 mA (MIN)
us BALANCED PROPAGATION DELAYS:
dtPLH ≅ tPHL
ros OPERATING VOLTAGE RANGE:
PVCC(OPR) = 2V to 5.5V
tes PIN AND FUNCTION COMPATIBLE WITH
le74 SERIES 541
os IMPROVED LATCH-UP IMMUNITY
ss LOW NOISE: VOLP = 0.9V (MAX.)
ObDESCRIPTION
-The 74VHC541 is an advanced high-speed
t(s)CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
cdouble-layer metal wiring C2MOS technology.
uThe 3 STATE control gate operates as two input
dAND such that if either G1 or G2 are high, all eight
rooutputs are in the high impedance state.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC541MTR
74VHC541TTR
In order to enhance PC board layout, the
74VHC541 offers a pinout having inputs and
outputs on opposite sides of the package.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Obsolete PFigure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 4
1/12
1 page  
74VHC541
Table 9: Dynamic Switching Characteristics
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
VOLP
VOLV
Dynamic Low
Voltage Quiet
Output (note 1, 2)
5.0
0.6 0.8
-0.8 -0.6
V
Dynamic High
VIHD Voltage Input
(note 1, 3)
5.0 CL = 50 pF 3.5
V
t(s)VILD
Dynamic Low
Voltage Input
(note 1, 3)
5.0
1.5 V
1) Worst case package.
c2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
u3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
d(VIHD), f=1MHz.
roFigure 3: Test Circuit
solete Product(s) - Obsolete PtPLH,tPHL
ObtPZL, tPLZ
TEST
SWITCH
Open
VCC
tPZH, tPHZ
GND
CL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
5/12
5 Page 
Table 10: Revision History
Date
12-Nov-2004
Revision
4
Description of Changes
Order Codes Revision - pag. 1.
74VHC541
Obsolete Product(s) - Obsolete Product(s)
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 74VHC541.PDF ] | |
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