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74LVT126PW 반도체 회로 부품 판매점

3.3V Quad buffer 3-State



NXP Semiconductors 로고
NXP Semiconductors
74LVT126PW 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LVT126
3.3V Quad buffer (3-State)
Product specification
Supersedes data of 1995 Dec 21
IC23 Data Handbook
1998 Feb 19
Philips
Semiconductors


74LVT126PW 데이터시트, 핀배열, 회로
Philips Semiconductors
3.3V Quad buffer (3-State)
Product specification
74LVT126
FEATURES
Quad bus interface
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Power-up 3-State
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The LVT126 is a high-performance BiCMOS product designed for
VCC operation at 3.3V.
This device combines low static and dynamic power dissipation with
high speed and high output drive.
The 74LVT126 device is a quad buffer that is ideal for driving bus
lines. The device features four Output Enables (OE0, OE1, OE2,
OE3), each controlling one of the 3-State outputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
An to Yn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 3.3V
VI = 0V or VCC
Outputs disabled; VO = 0V or 3.0V
Outputs disabled; VCC = 3.6V
TYPICAL
2.3
2.4
4
8
0.13
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP
14-Pin Plastic TSSOP
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT126 D
74LVT126 DB
74LVT126 PW
NORTH AMERICA
74LVT126 D
74LVT126 DB
74LVT126PW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN DESCRIPTION
PIN NUMBER
2, 5, 9, 12
3, 6, 8, 11
1, 4, 10, 13
7
14
SYMBOL
A0 – A3
Y0 – Y3
OE0 – OE3
GND
VCC
NAME AND FUNCTION
Data inputs
Data outputs
Output enable inputs
Ground (0V)
Positive supply voltage
PIN CONFIGURATION
OE0 1
A0 2
Y0 3
OE1 4
A1 5
Y1 6
GND 7
14 VCC
13 OE3
12 A3
11 Y3
10 OE2
9 A2
8 Y2
SA00031
LOGIC SYMBOL
1
OE0
2
A0
OE1
5
A1
4
10
OE2
9
A2
13
OE3
12
A3
3
Y0
6
Y1
8
Y2
11
Y3
SV00093
1998 Feb 19
2 853-1822 18991




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74LVT126PW buffer

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