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PDF 74LCX541 Data sheet ( Hoja de datos )
| Número de pieza | 74LCX541 | |
| Descripción | Low voltage CMOS octal bus buffer | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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74LCX541
Low voltage CMOS octal bus buffer (3-state)
with 5V tolerant inputs and outputs
Features
■ 5V tolerant inputs and outputs
■ High speed:
– tPD = 8.0ns (Max) at VCC = 3V
)■ Power down protection on inputs and outputs
t(s■ Symmetrical output impedance:
uc– |IOH| = IOL = 24mA (Min) at VCC = 3V
d■ PCI bus levels guaranteed at 24mA
ro■ Balanced propagation delays:
P– tPLH ≅ tPHL
te■ Operating voltage range:
ole– VCC (Opr) = 2.0V to 3.6V
s■ Pin and function compatible with
b74 series 541
O■ Latch-up performance exceeds
) -500mA (JESD 17)
t(s■ ESD performance:
c– HBM > 2000V
Obsolete Produ(MIL STD 883 method 3015); MM > 200V
SO-20
TSSOP20
Description
The 74LCX541 is a low voltage CMOS octal bus
buffer (non-inverted) fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to
5V signal environment for both inputs and
outputs.
The 3 STATE control gate operates as two input
AND such that if either G1 and G2 are high, all
eight outputs are in the high impedance state. In
order to enhance PC board layout the 74LCX541
offers a pinout having inputs and outputs on
opposite sides of the package.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Order codes
Part number
74LCX541MTR
74LCX541TTR
January 2007
Package
SO-20
TSSOP20
Rev 5
Packaging
Tape and reel
Tape and reel
1/17
www.st.com
17
1 page  
74LCX541
3 Logic states
Logic states
3.1 Truth table
Table 2. Truth table
Input
Output
G1 G2 An
Yn
HXX
Z
XHX
Z
Obsolete Product(s) - Obsolete Product(s)Note:
L
L
X : Do not care
Z : High impedance
L
L
H
L
L
H
5/17
5 Page 
74LCX541
8 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Obsolete Product(s) - Obsolete Product(s)
11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 74LCX541.PDF ] | |
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