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PDF W83178S Data sheet ( Hoja de datos )
| Número de pieza | W83178S | |
| Descripción | 100 MHZ 3-DIMM SDRAM BUFFER | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W83178S
100MHZ 3-DIMM SDRAM BUFFER
W83178S
Data Sheet Revision History
Pages
1 n.a.
2 n.a.
3
4
5
6
7
8
9
10
Dates Version
02/Apr
1.0
Version
On Web
n.a.
1.0
Main Contents
All of the versions before 0.50 are for internal use.
Change version and version on web site to 1.0
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date: Sep. 1998
- 1 - Revision 1.0
1 page  
W83178S
6.0 FUNTION DESCRIPTION
6.1 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the
latches for verification. All proceeding bytes must be sent to change one of the control bytes. The
2-wire control interface allows each clock output individually enabled or disabled. On power up, the
W83178S initializes with default register settings, and then it ptional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle.
Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and [1101 0010], command
code checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I2C registers after the string of data. The sequence order is as follows:
Publication Release Date: Sep. 1998
- 5 - Revision 1.0
5 Page 
10.0 PACKAGE DRAWING AND DIMENSIONS
28-SOP
W83178S
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Winbond for any damages resulting
from such improper use or sale.
- 11 -
Publication Release Date: Sep. 1998
Revision 1.0
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet W83178S.PDF ] | |
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