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Integrated Circuit Systems |
Integrated
Circuit
Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS83115 is a low skew, 1-to-16 LVCMOS/
LVTTL Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83115 single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The ICS83115 operates at full 3.3V supply mode over the
commercial temperature range. Guaranteed output and part-to-
part skew characteristics make the ICS83115 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
FEATURES
• 16 LVCMOS/LVTTL outputs
• 1 LVCMOS/LVTTL clock input
• Maximum output frequency: 200MHz
• All inputs are 5V tolerant
• Output skew: 250ps (maximum)
• Part-to-part skew: 800ps (maximum)
• Additive phase jitter, RMS: 0.09ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
OE2
VDD
4
IN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE1
4
GND
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
OE0
PIN ASSIGNMENT
OE1
Q0
Q1
Q2
VDD
VDD
Q3
Q4
GND
GND
Q5
Q6
Q7
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 OE2
27 Q15
26 Q14
25 Q13
24 VDD
23 VDD
22 Q12
21 Q11
20 GND
19 GND
18 Q10
17 Q9
16 Q8
15 OE0
ICS83115
28-Lead SSOP, 150mil
9.9mm x 3.9mm x 1.7mm body package
R Package
(Top View)
83115BR
www.icst.com/products/hiperclocks.html
1
REV. A SEPTEMBER 21, 2004
Integrated
Circuit
Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
OE1
Input
2, 3, 4, 7,
8, 11, 12, 13,
16, 17, 18,
21, 22, 25,
26, 27
Q0, Q1, Q2, Q3,
Q4, Q5, Q6, Q7,
Q8, Q9, Q10,
Q11, Q12, Q13,
Q14, Q15
Output
Pullup
Output enable. When LOW, forces outputs Q2 thru Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
5, 6, 23, 24
9, 10, 19, 20
VDD
GND
Power
Power
Core supply pin.
Power supply ground.
14 IN Input Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
15
OE0
Input
Pullup
Output enable. When LOW, forces outputs Q8 thru Q13 to
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
28
OE2
Input
Pullup
Output enable. When LOW, forces outputs Q0, Q1, Q15 and Q14 to
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
C
PD
RPULLUP
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
V = 3.465V
DD
VDD = 3.3V
Minimum Typical Maximum Units
4 pF
11 pF
51 KΩ
51 KΩ
5 7 12 Ω
TABLE 3. FUNCTION TABLE
Inputs
OE0
OE1
OE2
000
00 1
0 10
0 11
10 0
10
1
1 10
111
NOTE: OE0:OE2 are 5V tolerant.
Q0, Q1, Q14, Q15
(Control OE2)
HiZ
Active
HiZ
Active
HiZ
Active
HiZ
Active
Outputs
Q2:Q7
(Control OE1)
HiZ
HiZ
Active
Active
HiZ
HiZ
Active
Active
Q8:Q13
(Control OE0)
HiZ
HiZ
HiZ
HiZ
Active
Active
Active
Active
83115BR
www.icst.com/products/hiperclocks.html
2
REV. A SEPTEMBER 21, 2004
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