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PDF 830154I-08 Data sheet ( Hoja de datos )

Número de pieza 830154I-08
Descripción Over-Voltage Tolerant 1.5V 1:4 Fanout Buffer
Fabricantes IDT 
Logotipo IDT Logotipo



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Over-Voltage Tolerant 1.5V, 1:4
Fanout Buffer
830154I-08
Data Sheet
General Description
The 830154I-08 is an LVCMOS, over-voltage tolerant clock fanout
buffer targeted for clock generation in high-performance
telecommunication, networking and computing applications. The
device is optimized for low-skew clock distribution in low-voltage
applications. The input over-voltage tolerance enables using this
device in mixed-mode voltage applications. An output enable pin
controls whether the outputs are in the active or high impedance
state. Guaranteed output skew characteristics make the 830154I-08
ideal for those applications demanding well defined performance and
repeatability. The 830154I-08 is packaged in a small 8-TSSOP and
in an 8-SOIC package.
Features
Low-skew 1:4 fanout buffer
Supports 3.3V, 2.5V, 1.8V and 1.5V power supplies
LVCMOS input and output levels
3.6V Over-voltage tolerance at the clock and control inputs
Supports clock frequencies up to 160MHz
LVCMOS compatible control input for output disable
Output disabled to a high-impedance state
-40°C to 85°C ambient operating temperature
Available in lead-free RoHS 6 packages (8-TSSOP, 8-SOIC)
Block Diagram
CLK_IN
Pulldown
Pullup
OE
Q1
Pin Assignments
Q2
CLK_IN 1
8 OE
Q1 2
7 VDD
Q3
Q2 3
6 GND
Q3 4
5 Q4
Q4 830154AMI-08
8-SOIC, 150 mil
3.9mm x 4.9mm x 1.375mm package body
M-Package
Top View
830154AGI-08
8-TSSOP
4.4mm x 3.0mm x 0.925mm package body
G-Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 30, 2016

1 page




830154I-08 pdf
830154I-08 Data Sheet
Table 4H. LVCMOS DC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH Input High Voltage
VIL Input Low Voltage
CLK_IN
IIH Input High Current
OE
CLK_IN
IIL Input Low Current
OE
VOH Output High Voltage Q[4:1]
VOL Output Low Voltage Q[4:1]
VDD = VIN = 1.6V
VDD = VIN = 1.6V
VDD = 1.6V, VIN = 0V
VDD = 1.6V, VIN = 0V
IOH = -4mA
IOL = 4mA
0.65 * VDD
-0.3
-5
-150
0.75 * VDD
Typical
Maximum
3.6
0.35 * VDD
150
5
0.25 * VDD
Units
V
V
µA
µA
µA
µA
V
V
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tpLH
Output Frequency
Propagation Delay
(low to high transition); NOTE 1
tpHL
Propagation Delay
(high to low transition); NOTE 1
tPLZ, tPHZ
Disable Time
(active to high-impedance)
tPZL, tPZH
Enable Time
(high-impedance to disable)
tsk(o)
Output Skew; NOTE 2, 3
tsk(pp)
tjit
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
Minimum
0.7
Typical
Maximum
160
1.45
Units
MHz
ns
0.7 1.45 ns
10 ns
10
250
800
0.094
0.35 1.2
48 52
ns
ps
ps
ps
ns
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to FOUT 150MHz.
NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
©2016 Integrated Device Technology, Inc
5
Revision A March 30, 2016

5 Page





830154I-08 arduino
Applications Information
Recommendations for Unused Output Pins
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. There should be no
trace attached.
830154I-08 Data Sheet
©2016 Integrated Device Technology, Inc
11
Revision A March 30, 2016

11 Page







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