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PDF 74LCXH162244 Data sheet ( Hoja de datos )
| Número de pieza | 74LCXH162244 | |
| Descripción | LOW VOLTAGE CMOS 16-BIT BUS BUFFER | |
| Fabricantes | STMicroelectronics | |
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74LCXH162244
LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED :
tPD = 4.4 ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 12 mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s 26Ω SERIE RESISTORS IN OUTPUTS
s BUS HOLD PROVIDED ON DATA INPUT
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H162244
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX162244 is a low voltage CMOS 16 BIT
BUS BUFFER (NON-INVERTED) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
Any nG output control governs four BUS BUFF-
ERS. Output Enable input (nG) tied together gives
full 16-bit operation.
When nG is LOW, the outputs are on. When nG is
HIGH, the output are in high impedance state.
Active bus-hold circuitry is provided to hold un-
used or floating data inputs at a valid logic level.
This device is designed to be used with 3 state
memory address drivers, etc.
The device circuits is including 26Ω series resis-
tance in the outputs. These resistors permit to re-
duce line noise in high speed applications.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74LCXH162244TTR
February 2003
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1 page  
74LCXH162244
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
CL RL ts = tr -40 to 85 °C
-55 to 125 °C Unit
(V) (pF) (Ω) (ns) Min. Max. Min. Max.
tPLH tPHL Propagation Delay
Time
2.7
3.0 to 3.6
50 500 2.5
1.5
1.5
5.6
4.4
1.5
1.5
6.5
5.1
ns
tPZL tPZH Output Enable Time
2.7
1.5 6.3 1.5 7.2
50 500 2.5
ns
3.0 to 3.6
1.5 5.9 1.5 6.8
tPLZ tPHZ Output Disable Time
2.7
1.5 6.3 1.5 7.2
50 500 2.5
ns
3.0 to 3.6
1.5 5.9 1.5 6.8
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50 500 2.5
1.0
1.0 ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
CIN Input Capacitance
4 pF
COUT Output Capacitance
10 pF
CPD Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
50
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LCXH162244.PDF ] | |
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