PDF 9ZX21501C Data sheet ( Hoja de datos )

Número de pieza	9ZX21501C
Descripción	FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER
Fabricantes	IDT
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No Preview Available ! DATASHEET FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 9ZX21501C Description The 9ZX21501C is a 15-output version of the Intel DB1900Z Differential Buffer suitable for PCI-Express Gen3 or QPI applications. The part is backwards compatible to PCIe Gen1 and Gen2. A fixed external feedback maintains low drift for critical QPI applications. In bypass mode, the 9ZX21501C can provide outputs up to 400MHz. Recommended Application 15-output PCIe Gen3/QPI buffer with fixed feedback for Romley platforms Output Features • 15 - 0.7V current mode differential HCSL output pairs Features/Benefits • Fixed feedback path; 0ps input-to-output delay • 9 Selectable SMBus addresses; multiple devices can share same SMBus segment • 7 dedicated OE# pins; hardware control of outputs • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL BW; minimizes jitter peaking in downstream PLL's • Spread spectrum compatible; tracks spreading input clock for EMI reduction • SMBus Interface; unused outputs can be disabled • 100MHz & 133.33MHz PLL mode; legacy QPI support • Undriven differential outputs in Power Down mode for maximum power savings Functional Block Diagram Key Specifications • Cycle-to-cycle jitter: <50ps • Output-to-output skew: <65ps • Input-to-output delay: Fixed at 0 ps • Input-to-output delay variation: <50ps • Phase jitter: PCIe Gen3 <1ps rms • Phase jitter: QPI 9.6GB/s <0.2ps rms OE(5_8,10_12)# 7 DIF_IN DIF_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri SMBDAT SMBCLK Logic Z-PLL (SS Compatible) DFB_OUT DIF(14:0) IREF IDT® FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 1 9ZX21501C REV F 041613 1 page 9ZX21501C FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9ZX21501C. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage VDDA 3.3V Logic Supply Voltage VDD Input Low Voltage VIL Input High Voltage VIH Except for SMBus interface Input High Voltage VIHSMB SMBus clock and data pins Storage Temperature Ts Junction Temperature Tj Input ESD protection ESD prot Human Body Model 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. MIN TYP MAX UNITS NOTES 4.6 V 1,2 4.6 V 1,2 GND-0.5 V1 VDD+0.5V 5.5V V V 1 1 -65 150 °C 1 125 °C 1 2000 V1 Electrical Characteristics–Clock Input Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN Input High Voltage - DIF_IN VIHDIF Input Low Voltage - DIF_IN Input Common Mode Voltage - DIF_IN VILDIF VCOM Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Common Mode Input Voltage 600 VSS - 300 300 Input Amplitude - DIF_IN Input Slew Rate - DIF_IN VSWING dv/dt Peak to Peak value Measured differentially 300 0.4 Input Leakage Current IIN VIN = VDD , VIN = GND Input Duty Cycle dtin Measurement from differential wavefrom Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 1 Guaranteed by design and characterization, not 100% tested in production. 2Slew rate measured through +/-75mV window centered around differential zero -5 45 0 TYP 750 0 MAX 1150 UNITS NOTES mV 1 300 mV 1 1000 1450 8 5 55 125 mV mV V/ns uA % ps 1 1 1,2 1 1 1 IDT® FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 5 9ZX21501C REV F 041613 5 Page 9ZX21501C FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI General SMBus Serial Interface Information for 9ZX21501C How to Write • Controller (host) sends a start bit • Controller (host) sends the write address • IDT clock will acknowledge • Controller (host) sends the beginning byte location = N • IDT clock will acknowledge • Controller (host) sends the byte count = X • IDT clock will acknowledge • Controller (host) starts sending Byte N through Byte N+X-1 • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) IDT (Slave/Receiver) T starT bit Slave Address XX(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK O OO OO O Byte N + X - 1 ACK P stoP bit Note: XX(H) is defined by SMBus addess select pins. How to Read • Controller (host) will send a start bit • Controller (host) sends the write address XX(H) • IDT clock will acknowledge • Controller (host) sends the beginning byte location = N • IDT clock will acknowledge • Controller (host) will send a separate start bit • Controller (host) sends the read address YY(H) • IDT clock will acknowledge • IDT clock will send the data byte count = X • IDT clock sends Byte N+X-1 • IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) • Controller (host) will need to acknowledge each byte • Controller (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Read Operation Controller (Host) IDT (Slave/Receiver) T starT bit Slave Address XX(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address YY(H) RD ReaD ACK ACK ACK O O O N Not acknowledge P stoP bit Data Byte Count=X Beginning Byte N O O O Byte N + X - 1 IDT® FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 11 9ZX21501C REV F 041613 11 Page

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