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9DBL06 반도체 회로 부품 판매점

6-output 3.3V PCIe Zero-Delay Buffer



IDT 로고
IDT
9DBL06 데이터시트, 핀배열, 회로
6-output 3.3V PCIe Zero-Delay Buffer
9DBL06
Description
The 9DBL06 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DBL06 supports PCIe
Gen1-4 Common Clocked (CC) and PCIe Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85or 100transmission lines. The
9DBL06P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
6 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0641 default ZOUT = 100
9DBL0651 default ZOUT = 85
9DBL06P1 factory programmable defaults
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
DATASHEET
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 24 resistors compared to
standard PCIe devices
149mW typical power consumption (PLL [email protected]);
eliminates thermal concerns
VDDIO allows 30% power savings at optional 1.05V;
maximum power savings
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
Note: Default resistors are internal on xx41/xx51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL06 REVISION E 06/14/16
1 ©2016 Integrated Device Technology, Inc.


9DBL06 데이터시트, 핀배열, 회로
9DBL06 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri 1
30 NC
^vHIBW_BYPM_LOBW# 2
29 vOE3#
FB_DNC 3
28 DIF3#
FB_DNC# 4
VDDR3.3 5
9DBL0641/51/P1
27 DIF3
26 VDDIO
CLK_IN 6
epad is GND
25 VDDA3.3
CLK_IN# 7
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
40-VFQFPN, 5mm x 5mm 0.4mm pin pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition
from 2.1V to 3.135V in <300usec.
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
True O/P Comp. O/P
0
X
X
X
Low1
Low1
1
Running
0
X
Low1
Low1
1
Running
1
0
Running
Running
1
Running
1
1
Low1
Low1
1. The output state is set by B11[1:0] (Low/Low default)
2. If Bypass mode is selected, the PLL will be off, and outputs will be running.
PLL
Off
On2
On2
On2
Power Connections
PLL Operating Mode
Pin Number
VDD
5
11
16, 31
25
VDDIO
12,17,26,32,
39
GND
41
8
41
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
PLL Analog
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
2
REVISION E 06/14/16




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