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9DBV0741 반도체 회로 부품 판매점

7-output 1.8V HCSL Fanout Buffer



IDT 로고
IDT
9DBV0741 데이터시트, 핀배열, 회로
7-output 1.8V HCSL Fanout Buffer
w/Zo=100ohms
9DBV0741
DATASHEET
Description
The 9DBV0741 is a member of IDT's Full-Featured PCIe
family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100ohm
transmission lines.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
7 – 1-200MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
Additive cycle-to-cycle jitter <5ps
Output-to-output skew < 60ps
Additive phase jitter is <100fs rms for PCIe Gen3
Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
100ohm direct connect; saves 28 resistors and 48mm2
compared to standard HCSL
41mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0741 REVISION B 03/28/16 1 ©2016 Integrated Device Technology, Inc.


9DBV0741 데이터시트, 핀배열, 회로
9DBV0741 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri 1
30 NC
vOE6# 2
29 vOE3#
DIF6 3
28 DIF3#
DIF6# 4
VDDR1.8 5
CLK_IN 6
CLK_IN# 7
9DBV0741
connect epad to
GND
27 DIF3
26 VDDIO
25 VDD1.8
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SADR
0
M
1
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
40-VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
5mm x 5mm 0.4mm pin pitch
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low Low
Low Low
Running Running
Low Low
Power Connections
Pin Number
VDD
VDDIO
5
11
16, 25, 31
12,17,26,32,
39
GND
41
8
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
7-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS
2
REVISION B 03/28/16




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9DBV0741 buffer

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9DBV0741

7-output 1.8V HCSL Fanout Buffer - IDT