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9DBU0931 반도체 회로 부품 판매점

9 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer



IDT 로고
IDT
9DBU0931 데이터시트, 핀배열, 회로
9 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
9DBU0931
DATASHEET
Description
The 9DBU0931 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
9 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is <300fs rms for PCIe Gen 3
DIF additive phase jitter <350fs rms for SGMII
Block Diagram
Features/Benefits
LP-HCSL outputs; save 18 resistors compared to standard
HCSL outputs
47mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0931 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.


9DBU0931 데이터시트, 핀배열, 회로
9DBU0931 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1
36 DIF5#
vOE8# 2
35 DIF5
DIF8 3
34 vOE4#
DIF8# 4
33 DIF4#
VDDR1.5 5
CLK_IN 6
9DBU0931
32 DIF4
31 VDDIO
CLK_IN# 7
GNDR 8
epad is GND
30 VDDA1.5
29 GNDA
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG1.5 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND
pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resisto
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low Low
Low Low
Running
Running
Low Low
Power Connections
VDD
5
12
Pin Number
VDDIO
GND
8
9
Description
Input
receiver
analog
Digital Power
20,30,31,38 13,21,31,39,47 22,29,40 DIF outputs
Note: epad on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
9 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER
2
REVISION C 04/22/15




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9DBU0931 buffer

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9DBU0931

9 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer - IDT