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IDT |
2-output 3.3V PCIe Zero-Delay Buffer
9DBL02
Description
The 9DBL02 devices are 3.3V members of IDT's
Full-Featured PCIe family. The devices support PCIe Gen1-4
Common Clocked (CC) and PCIe Gen2 Separate Reference
Independent Spread (SRIS) systems. It offers a choice of
integrated output terminations providing direct connection to
85 or 100 transmission lines. The 9DBL02P1 can be
factory programmed with a user-defined power up default
SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
• 2 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
• 9DBL0242 default ZOUT = 100
• 9DBL0252 default ZOUT = 85
• 9DBL02P2 factory programmable defaults
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• PCIe Gen1-2-3-4 CC compliant in ZDB mode
• PCIe Gen2 SRIS compliant in ZDB mode
• Supports PCIe Gen2-3 SRIS in fan-out mode
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew < 50ps
• Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
• Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
DATASHEET
Features/Benefits
• Direct connection to 100 (xx42) or 85 (xx52)
transmission lines; saves 8 resistors compared to standard
PCIe devices
• 100mW typical power consumption in PLL mode; minimal
power consumption
• SMBus-selectable features allows optimization to customer
requirements:
– control input polarity
– control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
• Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device operation
• Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.
9DBL02 OCTOBER 6, 2016
1 ©2016 Integrated Device Technology, Inc.
9DBL02 DATASHEET
Pin Configuration
FB_DNC 1
FB_DNC# 2
VDDR3.3 3
CLK_IN 4
CLK_IN# 5
GNDDIG 6
24 23 22 21 20 19
9DBL0242/52/P2
connect epad to
GND
7 8 9 10 11 12
18 DIF1#
17 DIF1
16 VDDA3.3
15 vOE0#
14 DIF0#
13 DIF0
SMBus Address Selection Table
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND
pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down
resistor
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition
from 2.1V to 3.135V in <300usec.
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OE bit
OEx# Pin
DIFx/DIFx#
True O/P Comp. O/P
0
X
X
X
Low1
Low1
1
Running
1
0
Running
Running
1
Running
1
1 Disabled1 Disabled1
1
Running
0
X Disabled1 Disabled1
1. The output state is set by B11[1:0] (Low/Low default)
2. Input polarities defined as default values for xx41/xx51 devices.
3. If Bypass mode is selected, the PLL will be off, and outputs will be running.
PLL
Off
On3
On3
On3
Power Connections
PLL Operating Mode
Pin Number
VDD
3
8
10,21
16
GND
25
6
25
25
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
2
OCTOBER 6, 2016
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