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LVDS Output Fanout Buffer



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IDT
8SLVD2102 데이터시트, 핀배열, 회로
Dual 1:2, LVDS Output Fanout Buffer
8SLVD2102
DATA SHEET
General Description
The 8SLVD2102 is a high-performance differential dual 1:2 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVD2102 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2102 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
independent buffers with two low skew outputs each are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Two 1:2, low skew, low additive jitter LVDS fanout buffers
Two differential clock inputs
Differential pairs can accept the following differential input
levels: LVDS and LVPECL
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (maximum)
Propagation delay: 300ps (maximum)
Low additive phase jitter: 200fs, RMS (maximum);
fREF = 156.25MHz, VPP = 1V, VCMR = 1V,
Integration Range 10kHz - 20MHz
2.5V supply voltage
Maximum device current consumption (IDD): 90mA
Lead-free (RoHS 6) 16-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Block Diagram
VDD
PCLKA
nPCLKA
PCLKB
nPCLKB
VDD
VREF
EN
Voltage
VDD Reference
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pin Assignment
16 15 14 13
GND 1
12 nQA1
EN 2
PCLKB 3
8SLVD2102I
8XXXXXX
11 QA1
10 nQA0
nPCLKB 4
9 QA0
56 7 8
16-pin, 3.0mm x 3.0mm VFQFN Package
8SLVD2102 REVISION 2 11/11/15 1 ©2015 Integrated Device Technology, Inc.


8SLVD2102 데이터시트, 핀배열, 회로
8SLVD2102 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
GND
Power
Power supply ground.
2
EN
Input
Pullup/
Pulldown Output enable pin.
3
PCLKB
Input
Pulldown Non-inverting differential clock/data input.
4
nPCLKB
Input
Pullup/
Pulldown Inverting differential clock/data input. VDD/2 default when left floating.
5 VDD Power
Power supply pin.
6
PCLKA
Input
Pulldown Non-inverting differential clock/data input.
7
nPCLKA
Input
Pullup/
Pulldown Inverting differential clock/data input. VDD/2 default when left floating.
8
9, 10
VREF
QA0, nQA0
Output
Output
Bias voltage reference for the PCLKx, nPCLKx inputs.
Differential output pair. LVDS interface levels.
11, 12
QA1, nQA1 Output
Differential output pair. LVDS interface levels.
13, 14
QB0, nQB0 Output
Differential output pair. LVDS interface levels.
15, 16
QB1, nQB1 Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
Input Capacitance
Input Pulldown
Resistor
PCLK inputs
RPULLUP
Input Pullup
Resistor
PCLK inputs
RPULLDOWN
Input Pulldown
Resistor
EN input
RPULLUP
Input Pullup
Resistor
EN input
Test Conditions
Minimum
Typical
2
51
Maximum
Units
pF
k
51 k
51 k
51 k
Table 3. EN Input Selection Function Table
Input
EN Operation
0 (Low) Outputs are disabled and outputs are static at Qx = 0 (low level) and nQx = 1 (high level).
1 (High)
Bank A outputs are enabled and Bank B outputs are disabled at the following static levels: QBx = 0 (low level) and
nQBx = 1 (high level).
Open All outputs enabled.
NOTE: EN is an asynchronous control.
DUAL 1:2, LVDS OUTPUT FANOUT BUFFER
2
REVISION 2 11/11/15




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